74HC42

更新时间： 2024-02-13 12:18:15

品牌	Logo	应用领域
恩智浦 - NXP		/
页数	文件大小	规格书
6页	46K
描述
BCD to decimal decoder 1-of-10

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技术参数
数据手册

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74HC42 技术参数

生命周期：	Obsolete	包装说明：	TSSOP,
Reach Compliance Code：	unknown	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.71
系列：	HC/UH	输入调节：	STANDARD
JESD-30 代码：	R-PDSO-G16	长度：	5 mm
负载电容（CL）：	50 pF	逻辑集成电路类型：	DECIMAL DECODER/DRIVER
功能数量：	1	端子数量：	16
最高工作温度：	125 °C	最低工作温度：	-40 °C
输出极性：	INVERTED	封装主体材料：	PLASTIC/EPOXY
封装代码：	TSSOP	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	传播延迟（tpd）：	45 ns
认证状态：	Not Qualified	座面最大高度：	1.1 mm
最大供电电压 (Vsup)：	6 V	最小供电电压 (Vsup)：	2 V
标称供电电压 (Vsup)：	5 V	表面贴装：	YES
技术：	CMOS	温度等级：	AUTOMOTIVE
端子形式：	GULL WING	端子节距：	0.65 mm
端子位置：	DUAL	宽度：	4.4 mm
Base Number Matches：	1

74HC42 数据手册

Philips Semiconductors

Product speciﬁcation

BCD to decimal decoder (1-of-10)

74HC/HCT42

The 74HC/HCT42 decoders accept four active HIGH BCD

inputs and provide 10 mutually exclusive active LOW

outputs. The active LOW outputs facilitate addressing

other MSI circuits with active LOW input enables.

FEATURES

• Mutually exclusive outputs

• 1-of-8 demultiplexing capability

• Outputs disabled for input codes above nine

• Output capability: standard

• I_CCcategory: MSI

The logic design of the “42” ensures that all outputs are

HIGH when binary codes greater than nine are applied to

the inputs.

The most significant input (A₃) produces an useful inhibit

function when the “42” is used as a 1-of-8 decoder. The A₃

input can also be used as the data input in an 8-output

demultiplexer application.

GENERAL DESCRIPTION

The 74HC/HCT42 are high-speed Si-gate CMOS devices

and are pin compatible with low power Schottky TTL

(LSTTL). They are specified in compliance with JEDEC

standard no. 7A.

QUICK REFERENCE DATA

GND = 0 V; T_amb= 25 °C; t_r= t_f= 6 ns

TYPICAL

SYMBOL

PARAMETER

CONDITIONS

UNIT

HCT

t_PHL/ t_PLH

C_I

propagation delay A_nto Y_n

input capacitance

C_L= 15 pF; V_CC= 5 V 14

3.5

C_PD

power dissipation capacitance per package

notes 1 and 2

Notes

1. C_PDis used to determine the dynamic power dissipation (P_Din µW):

P_D= C_PD× V_CC²× f_i+ ∑ (C_L× V_CC²× f_o) where:

f_i= input frequency in MHz

f_o= output frequency in MHz

∑ (C_L× V_CC²× f_o) = sum of outputs

C_L= output load capacitance in pF

V_CC= supply voltage in V

2. For HC the condition is V_I= GND to V_CC

For HCT the condition is V_I= GND to V_CC− 1.5 V

ORDERING INFORMATION

See “74HC/HCT/HCU/HCMOS Logic Package Information”.

December 1990

123 4 5 6

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