Datasheet > 74HC4059U

74HC4059U

更新时间： 2023-01-03 02:47:48

品牌	Logo	应用领域
恩智浦 - NXP		/
页数	文件大小	规格书
20页	131K
描述
IC HC/UH SERIES, ASYN POSITIVE EDGE TRIGGERED BIDIRECTIONAL DIVIDE BY N COUNTER, UUC, DIE, Counter

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数据手册

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74HC4059U 数据手册

Philips Semiconductors

Product speciﬁcation

Programmable divide-by-n counter

74HC/HCT4059

QUICK REFERENCE DATA

GND = 0 V; T_amb= 25 °C; t_r= t_f= 6 ns

SYMBOL

PARAMETER

CONDITIONS

TYPICAL

HC HCT

UNIT

t_PHL/ t_PLH

propagation delay CP to Q

maximum clock frequency

input capacitance

C_L= 15 pF; V_CC= 5 V 18

3.5

f_max

C_I

MHz

3.5

C_PD

power dissipation capacitance per package notes 1 and 2

Notes

1. C_PDis used to determine the dynamic power dissipation (P_Din µW):

P_D= C_PD× V_CC²× f_i+ ∑ (C_L× V_CC²× f_o) where:

f_i= input frequency in MHz

f_o= output frequency in MHz

∑ (C_L× V_CC²× f_o) = sum of outputs

C_L= output load capacitance in pF

V_CC= supply voltage in V

2. For HC the condition is V_I= GND to V_CC

For HCT the condition is V_I= GND to V_CC− 1.5 V

ORDERING INFORMATION

PACKAGE

TYPE

NUMBER

NAME

DESCRIPTION

VERSION

74HC4059N3;

74HCT4059N3

DIP24

plastic dual in-line package; 24 leads (300 mil)

SOT222-1

74HC4059N;

74HCT4059N

DIP24

SO24

plastic dual in-line package; 24 leads (600 mil)

SOT101-1

SOT137-1

74HC4059D;

74HCT4059D

plastic small outline package; 24 leads; body width 7.5 mm

1998 Jul 08

1 2 345 6 7...20

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