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74HC390N,652 PDF预览

74HC390N,652

更新时间： 2024-01-30 20:44:56
品牌 Logo 应用领域
恩智浦 - NXP 光电二极管逻辑集成电路触发器
页数 文件大小 规格书
7页 47K
描述
74HC(T)390 - Dual decade ripple counter DIP 16-Pin

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74HC390N,652 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：DIP包装说明：DIP, DIP16,.3
针数：16Reach Compliance Code：compliant
HTS代码：8542.39.00.01风险等级：7.18
其他特性：DIVIDE BY 2 AND DIVIDE BY 5 FUNCTIONS计数方向：UP
系列：HC/UHJESD-30 代码：R-PDIP-T16
长度：21.6 mm负载电容（CL）：50 pF
负载/预设输入：NO逻辑集成电路类型：DECADE COUNTER
最大频率@ Nom-Sup：20000000 Hz最大I（ol）：0.004 A
工作模式：ASYNCHRONOUS位数：3
功能数量：4端子数量：16
最高工作温度：125 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：DIP
封装等效代码：DIP16,.3封装形状：RECTANGULAR
封装形式：IN-LINE峰值回流温度（摄氏度）：260
电源：2/6 V传播延迟（tpd）：63 ns
认证状态：Not Qualified座面最大高度：4.7 mm
子类别：Counters最大供电电压 (Vsup)：6 V
最小供电电压 (Vsup)：2 V标称供电电压 (Vsup)：5 V
表面贴装：NO技术：CMOS
温度等级：AUTOMOTIVE端子面层：NICKEL/PALLADIUM/GOLD (NI/PD/AU)
端子形式：THROUGH-HOLE端子节距：2.54 mm
端子位置：DUAL处于峰值回流温度下的最长时间：30
触发器类型：NEGATIVE EDGE宽度：7.62 mm
最小 fmax：20 MHzBase Number Matches：1

74HC390N,652 数据手册

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Philips Semiconductors  
Product specification  
Dual decade ripple counter  
74HC/HCT390  
decade or bi-quinary configuration, since they share a  
common master reset input (nMR). If the two master reset  
inputs (1MR and 2MR) are used to simultaneously clear all  
8 bits of the counter, a number of counting configurations  
are possible within one package. The separate clocks  
(nCP0 and nCP1 ) of each section allow ripple counter or  
frequency division applications of divide-by-2, 4, 5, 10, 20,  
25, 50 or 100.  
FEATURES  
• Two BCD decade or bi-quinary counters  
• One package can be configured to divide-by-2, 4, 5, 10,  
20, 25, 50 or 100  
• Two master reset inputs to clear each decade counter  
individually  
• Output capability: standard  
• ICC category: MSI  
Each section is triggered by the HIGH-to-LOW transition of  
the clock inputs (nCP0 and nCP1 ). For BCD decade  
operation, the nQ0 output is connected to the nCP1 input  
of, the divide-by-5 section. For bi-quinary decade  
operation, the nQ3 output is connected to the nCP0 input  
and nQ0 becomes the decade output.  
GENERAL DESCRIPTION  
The 74HC/HCT390 are high-speed Si-gate CMOS devices  
and are pin compatible with low power Schottky TTL  
(LSTTL). They are specified in compliance with JEDEC  
standard no. 7A.  
The master reset inputs (1MR and 2MR) are active HIGH  
asynchronous inputs to each decade counter which  
operates on the portion of the counter identified by the “1”  
and “2” prefixes in the pin configuration. A HIGH level on  
the nMR input overrides the clocks and sets the four  
outputs LOW.  
The 74HC/HCT390 are dual 4-bit decade ripple counters  
divided into four separately clocked sections. The counters  
have two divide-by-2 sections and two divide-by-5  
sections. These sections are normally used in a BCD  
QUICK REFERENCE DATA  
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns  
TYPICAL  
SYMBOL  
PARAMETER  
propagation delay  
CONDITIONS  
UNIT  
HC HCT  
tPHL/ tPLH  
CL = 15 pF; VCC = 5 V  
nCP0 to nQ0  
14  
18  
19  
26  
19  
18  
61  
3.5  
21  
ns  
nCP1 to nQ1  
15  
23  
15  
16  
66  
3.5  
20  
ns  
nCP1 to nQ2  
ns  
nCP1 to nQ3  
ns  
nMR to Qn  
ns  
fmax  
CI  
maximum clock frequency nCP0, nCP1  
input capacitance  
MHz  
pF  
pF  
CPD  
power dissipation capacitance per counter  
notes 1 and 2  
Notes  
1. CPD is used to determine the dynamic power dissipation (PD in µW):  
2
PD = CPD × VCC2 × fi + ∑ (CL × VCC × fo) where:  
fi = input frequency in MHz  
fo = output frequency in MHz  
2
∑ (CL × VCC × fo) = sum of outputs  
CL = output load capacitance in pF  
VCC = supply voltage in V  
2. For HC the condition is VI = GND to VCC  
For HCT the condition is VI = GND to VCC −1.5 V  
December 1990  
2
1234567

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