Datasheet > 74HC2G86-Q100

74HC2G86-Q100

更新时间： 2022-02-26 13:18:37

品牌	Logo	应用领域
安世 - NEXPERIA		/
页数	文件大小	规格书
11页	215K
描述
Dual 2-input EXCLUSIVE-OR gate

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74HC2G86-Q100 数据手册

Nexperia

74HC2G86-Q100; 74HCT2G86-Q100

Dual 2-input EXCLUSIVE-OR gate

11.1. Waveforms and test circuit

nA, nB input

GND

PLH

PHL

nY output

TLH

THL

001aak020

Measurement points are given in Table 9.

V_OLand V_OHare typical output voltage levels that occur with the output load.

Fig. 5. Propagation delay data input (nA, nB) to data output (nY) and transition time output (nY)

Table 9. Measurement points

Type

Input

V_M

Output

V_M

V_X

V_Y

74HC2G86-Q100

74HCT2G86-Q100

0.5V_CC

1.3 V

0.5V_CC

1.3 V

0.1V_CC

0.9V_CC

90 %

negative

pulse

10 %

0 V

90 %

positive

pulse

10 %

0 V

open

DUT

001aad983

Test data is given in Table 10.

Definitions for test circuit:

R_T= Termination resistance should be equal to output impedance Z_oof the pulse generator;

C_L= Load capacitance including jig and probe capacitance; R_L= Load resistance and S1 = Test selection switch.

Fig. 6. Test circuit for measuring switching times

Table 10. Test data

Type

Input

V_I

Load

C_L

S1 position

t_PHL, t_PLH

open

t_r, t_f

R_L

74HC2G86-Q100 GND to V_CC

74HCT2G86-Q100 GND to 3 V

≤ 6 ns

50 pF

1 kΩ

open

74HC_HCT2G86_Q100

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 2 — 18 December 2018

6 / 11

1...3 4 567 8 9...11

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