IDT74FCT388915T
3.3VLOWSKEWPLL-BASEDCMOSCLOCKDRIVER(3-STATE)
COMMERCIALTEMPERATURERANGE
TESTCIRCUITSANDWAVEFORMS
6.0V
VCC
VCC
VCC
GND
100Ω
500Ω
500Ω
IN
VOUT
V
VOUT
IN
V
Pulse
Generator
Pulse
Generator
D.U.T.
D.U.T.
20pF
CL
100Ω
RT
RT
50Ω to VCC/2, CL = 20pF
Enable and Disable Test Circuit
1.5V
SYNC INPUT
(SYNC (1) or
SYNC (0))
t
CYCLE
SYNC INPUT
tPD
VCC/2
VCC/2
FEEDBACK
INPUT
Q/2 OUTPUT
t
t
t
SKEWf
t
SKEWf
SKEWr
t
SKEWr
VCC/2
SKEWALL
Q0-Q4
OUTPUTS
t
CYCLE "Q" OUTPUTS
VCC/2
VCC/2
Q5 OUTPUT
2Q OUTPUT
Propagation Delay, Output Skew
(These waveforms represent the configuration of Figure 3a)
NOTES:
1. The FCT388915T aligns rising edges of the FEEDBACK input and SYNC input, therefore the SYNC input does not require a 50% duty cycle.
2. All skew specs are measured between the VCC/2 crossing point of the appropriate output edges. All skews are specified as "windows", not as ± deviation around a center point.
3. If a Q ouput is connected to the FEEDBACK input (this situation is not shown), the Q output frequency would match the SYNC input frequency, the 2Q output would run at twice
the SYNC frequency and the Q/2 output would run at half the SYNC frequency.
ENABLE
DISABLE
SWITCHPOSITION
3V
CONTROL
INPUT
1.5V
0V
Test
Switch
tPZL
tPLZ
Disable Low
Enable Low
6V
3V
1.5V
3V
OUTPUT
NORMALLY
LOW
SWITCH
6V
0.3V
0.3V
VOL
Disable High
Enable High
GND
tPZH
tPHZ
VOH
OUTPUT
NORMALLY
HIGH
SWITCH
GND
1.5V
0V
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
0V
RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
Enable and Disable Times
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
2. Pulse Generator for All Pulses: tF ≤ 2.5ns; tR ≤ 2.5ns.
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