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74F573SCQR PDF预览

74F573SCQR

更新时间: 2024-01-02 12:33:31
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 锁存器
页数 文件大小 规格书
6页 62K
描述
Bus Driver, F/FAST Series, 1-Func, 8-Bit, True Output, TTL, PDSO20, 0.150 INCH, SOIC-20

74F573SCQR 技术参数

是否Rohs认证: 符合生命周期:Obsolete
包装说明:SOP, SOP20,.3Reach Compliance Code:compliant
风险等级:5.84JESD-30 代码:R-PDSO-G20
逻辑集成电路类型:D LATCH最大I(ol):0.024 A
位数:8功能数量:1
端子数量:20最高工作温度:70 °C
最低工作温度:输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP20,.3封装形状:RECTANGULAR
封装形式:SMALL OUTLINE包装方法:TAPE AND REEL
电源:5 V最大电源电流(ICC):55 mA
Prop。Delay @ Nom-Sup:8 ns认证状态:Not Qualified
子类别:FF/Latches标称供电电压 (Vsup):5 V
表面贴装:YES技术:TTL
温度等级:COMMERCIAL端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
Base Number Matches:1

74F573SCQR 数据手册

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Unit Loading/Fan Out  
Input IIH/IIL  
U.L.  
Pin Names  
Description  
Output IOH/IOL  
HIGH/LOW  
1.0/1.0  
D0–D7  
Data Inputs  
20 µA/0.6 mA  
20 µA/0.6 mA  
LE  
Latch Enable Input (Active HIGH)  
1.0/1.0  
3-STATE Output Enable Input (Active LOW)  
1.0/1.0  
20 µA/0.6 mA  
OE  
O0–O7  
3-STATE Latch Outputs  
150/40(33.3)  
3 mA/24 mA (20 mA)  
Functional Description  
Function Table  
The 74F573 contains eight D-type latches with 3-state out-  
put buffers. When the Latch Enable (LE) input is HIGH,  
data on the Dn inputs enters the latches. In this condition  
Inputs  
Outputs  
OE  
L
LE  
H
H
L
D
H
L
O
H
the latches are transparent, i.e., a latch output will change  
state each time its D input changes. When LE is LOW the  
latches store the information that was present on the D  
inputs a setup time preceding the HIGH-to-LOW transition  
of LE. The 3-state buffers are controlled by the Output  
Enable (OE) input. When OE is LOW, the buffers are in the  
bi-state mode. When OE is HIGH the buffers are in the high  
impedance mode but this does not interfere with entering  
new data into the latches.  
L
L
L
X
X
O0  
Z
H
X
H = HIGH Voltage Level  
L = LOW Voltage Level  
X = Immaterial  
O
= Value stored from previous clock cycle  
0
Logic Diagram  
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.  
www.fairchildsemi.com  
2

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