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74F573

更新时间： 2024-02-12 22:03:00
品牌 Logo 应用领域
恩智浦 - NXP 锁存器
页数 文件大小 规格书
14页 111K
描述
Octal transparent latch 3-State

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74F573 技术参数

是否Rohs认证： 符合生命周期：Obsolete
包装说明：SOP, SOP20,.3Reach Compliance Code：compliant
风险等级：5.84JESD-30 代码：R-PDSO-G20
逻辑集成电路类型：D LATCH最大I（ol）：0.024 A
位数：8功能数量：1
端子数量：20最高工作温度：70 °C
最低工作温度：输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：SOP
封装等效代码：SOP20,.3封装形状：RECTANGULAR
封装形式：SMALL OUTLINE包装方法：TAPE AND REEL
电源：5 V最大电源电流（ICC）：55 mA
Prop。Delay @ Nom-Sup：8 ns认证状态：Not Qualified
子类别：FF/Latches标称供电电压 (Vsup)：5 V
表面贴装：YES技术：TTL
温度等级：COMMERCIAL端子形式：GULL WING
端子节距：1.27 mm端子位置：DUAL
Base Number Matches：1

74F573 数据手册

 浏览型号74F573的Datasheet PDF文件第1页浏览型号74F573的Datasheet PDF文件第3页浏览型号74F573的Datasheet PDF文件第4页浏览型号74F573的Datasheet PDF文件第5页浏览型号74F573的Datasheet PDF文件第6页浏览型号74F573的Datasheet PDF文件第7页 
Philips Semiconductors  
Product specification  
Latch/flip-flop  
74F573/74F574  
74F573 Octal Transparent Latch (3-State)  
74F574 Octal D Flip-Flop (3-State)  
The 74F574 is functionally identical to the 74F374 but has a  
broadside pinout configuration to facilitate PC board layout and  
allow easy interface with microprocesors.  
FEATURES  
• 74F573 is broadside pinout version of 74F373  
• 74F574 is broadside pinout version of 74F374  
It is an 8-bit, edge triggered register coupled to eight 3-State output  
buffers. The two sections of the device are controlled independently  
by the clock (CP) and Output Enable (OE) control gates.  
• Inputs and Outputs on opposite side of package allow easy  
interface to Microprocessors  
The register is fully edge-triggered. The state of each D input, one  
setup time before the Low-to-High clock transition is transferred to  
the corresponding flip-flop’s Q output.  
• Useful as an Input or Output port for Microprocessors  
• 3-State Outputs for Bus interfacing  
• Common Output Enable  
The 3-State output buffers are designed to drive heavily loaded  
3-State buses, MOS memories, or MOS microprocessors. The  
active Low Output Enable (OE) controls all eight 3-State buffers  
independently of the latch operation. When OE is Low, the latched  
or transparent data appears at the outputs. When OE is High, the  
outputs are in high impedance “off” state, which means they will  
neither drive nor load the bus.  
• 74F563 and 74F564 are inverting version of 74F573 and 74F574  
respectively  
• 3-State Outputs glitch free during power-up and power-down  
• These are High-Speed replacements for N8TS805 and N8TS806  
DESCRIPTION  
TYPICAL SUPPLY  
TYPICAL  
PROPAGATION DELAY  
The 74F573 is an octal transparent latch coupled to eight 3-State  
output buffers. The two sections of the device are controlled  
independently by Enable (E) and Output Enable (OE) control gates.  
CURRENT  
(TOTAL)  
TYPE  
74F573  
5.0ns  
35mA  
The 74F573 is functionally identical to the 74F373 but has a  
broadside pinout configuration to facilitate PC board layout and  
allow easy interface with microprocessors.  
TYPICAL SUPPLY  
CURRENT  
TYPE  
TYPICAL f  
MAX  
The data on the D inputs is transferred to the latch outputs when the  
Enable (E) input is High. The latch remains transparent to the data  
input while E is High and stores the data that is present one setup  
time before the High-to-Low enable transition.  
(TOTAL)  
74F574  
180MHz  
50mA  
ORDERING INFORMATION  
The 3-State output buffers are designed to drive heavily loaded  
3-State buses, MOS memories, or MOS microprocessors. The  
active Low Output Enable (OE) controls all eight 3-State buffers  
independent to the latch operation. When OE is Low, the latched or  
transparent data appears at the outputs. When OE is High, the  
outputs are in high impedance “off” state, which means they will  
neither drive nor load the bus.  
COMMERCIAL RANGE  
= 5V ±10%,  
V
DESCRIPTION  
PKG DWG #  
CC  
T
amb  
= 0°C to +70°C  
20-Pin Plastic DIP  
20-Pin Plastic SOL  
20-Pin Plastic SSOP  
N74F573N, N74F574N SOT146-1  
N74F573D, N74F574D SOT163-1  
N74F573DB  
SOT339-1  
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE  
74F (U.L.)  
HIGH/LOW  
LOAD VALUE  
HIGH/LOW  
PINS  
DESCRIPTION  
D0 - D7  
Data inputs  
1.0/1.0  
1.0/1.0  
1.0/1.0  
1.0/1.0  
150/40  
20µA/0.6mA  
20µA/0.6mA  
20µA/0.6mA  
20µA/0.6mA  
3.0mA/24mA  
E (74F573)  
OE  
Latch Enable input (active falling edge)  
Output Enable input (active Low)  
Clock Pulse input (active rising edge)  
3-State outputs  
CP (74F574)  
Q0 - Q7  
NOTE: One (1.0) FAST Unit Load is defined as: 20µA in the High state and 0.6mA in the Low state.  
2
1989 Oct 16  
853-0083 97897  
1234567...14

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