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74F534 PDF预览

74F534

更新时间: 2024-01-15 06:05:31
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD /
页数 文件大小 规格书
6页 63K
描述
Octal D-Type Flip-Flop with 3-STATE Outputs

74F534 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:SOIC包装说明:5.30 MM, EIAJ TYPE2, SOP-20
针数:20Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.43
Is Samacsys:N系列:F/FAST
JESD-30 代码:R-PDSO-G20JESD-609代码:e3
长度:12.6 mm逻辑集成电路类型:BUS DRIVER
最大频率@ Nom-Sup:70000000 Hz最大I(ol):0.024 A
湿度敏感等级:1位数:8
功能数量:1端口数量:2
端子数量:20最高工作温度:70 °C
最低工作温度:输出特性:3-STATE
输出极性:INVERTED封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP20,.3
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
包装方法:TAPE AND REEL峰值回流温度(摄氏度):260
电源:5 V最大电源电流(ICC):86 mA
传播延迟(tpd):10 ns认证状态:Not Qualified
座面最大高度:2.1 mm子类别:FF/Latches
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:TTL温度等级:COMMERCIAL
端子面层:Matte Tin (Sn)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED触发器类型:POSITIVE EDGE
宽度:5.3 mmBase Number Matches:1

74F534 数据手册

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Unit Loading/Fan Out  
Input IIH/IIL  
U.L.  
Pin Names  
Description  
Output IOH/IOL  
HIGH/LOW  
1.0/1.0  
D0–D7  
CP  
Data Inputs  
20 µA/0.6 mA  
20 µA/0.6 mA  
Clock Pulse Input (Active Rising Edge)  
3-STATE Output Enable Input (Active LOW)  
Complementary 3-STATE Outputs  
1.0/1.0  
OE  
1.0/1.0  
20 µA/0.6 mA  
O0–O7  
150/40(33.3)  
3 mA/24 mA (20 mA)  
Function Table  
Functional Description  
The 74F534 consists of eight edge-triggered flip-flops with  
individual D-type inputs and 3-STATE complementary out-  
puts. The buffered clock and buffered Output Enable are  
common to all flip-flops. The eight flip-flops will store the  
state of their individual D inputs that meet the setup and  
hold times requirements on the LOW-to-HIGH clock (CP)  
transition. With the Output Enable (OE) LOW, the contents  
of the eight flip-flops are available at the outputs. When the  
OE is HIGH, the outputs go to the high impedance state.  
Operation of the OE input does not affect the state of the  
flip-flops.  
Inputs  
Output  
CP  
OE  
L
D
H
L
O
L
L
H
L
L
X
O0  
Z
X
H
X
H = HIGH Voltage Level  
X = Immaterial  
L = LOW Voltage Level  
Z = High Impedance  
= LOW-to-HIGH Clock Transition  
O
= Value stored from previous clock cycle  
0
Logic Diagram  
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.  
www.fairchildsemi.com  
2

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