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74F525

更新时间: 2024-02-25 11:11:38
品牌 Logo 应用领域
美国国家半导体 - NSC 计数器
页数 文件大小 规格书
10页 174K
描述
Programmable Counter

74F525 技术参数

生命周期:Obsolete零件包装代码:DIP
包装说明:DIP,针数:28
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.83其他特性:PROGRAMMABLE 16 BIT DOWN COUNTER; 8 MODES OF OPERATION; DIVIDE BY N AND N/2 OUTPUTS AVAILABLE
计数方向:DOWN系列:F/FAST
JESD-30 代码:R-PDIP-T28负载/预设输入:YES
逻辑集成电路类型:DIVIDE BY N COUNTER工作模式:ASYNCHRONOUS
功能数量:1端子数量:28
最高工作温度:70 °C最低工作温度:
封装主体材料:PLASTIC/EPOXY封装代码:DIP
封装形状:RECTANGULAR封装形式:IN-LINE
传播延迟(tpd):22 ns认证状态:Not Qualified
最大供电电压 (Vsup):5.25 V最小供电电压 (Vsup):4.75 V
标称供电电压 (Vsup):5 V表面贴装:NO
技术:TTL温度等级:COMMERCIAL
端子形式:THROUGH-HOLE端子位置:DUAL
触发器类型:POSITIVE EDGE最小 fmax:60 MHz

74F525 数据手册

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Functional Description (Continued)  
MODE 6: Retriggerable Synchronous One-Shot  
Function Table  
When XTR is HIGH, the data in the data latches is loaded  
into the counter upon the positive edge of CP. The negative  
edge of XTR enables the count-down to begin with the next  
positive edge of CP, wehre Q, normally LOW, is then  
brought HIGH and the counter is decremented when the  
count reaches zero, Q is brought LOW, and Q/2 is toggled.  
Bringing XTR HIGH during the count-down will allow the  
data in the data latches to be loaded into the counter with  
the next positive edge of CP, but will not affect Q. See Fig-  
ure 4. NOTE that the pulse width of Q will be N-1 clock  
cycles, where N is the number loaded into the counter.  
M
M
M
0
Function  
2
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Mode 0  
Mode 1  
Mode 2  
Mode 3  
Mode 4  
Mode 5  
Mode 6  
Mode 7  
e
results.  
N
1 should not be used as this may cause unpredictable  
MODE 4: Interval Timer, Pulse Output with Count Hold  
MODE 7: Frequency Generator  
While XTR is HIGH, the data in the data latches is loaded  
into the counter upon the next positive edge of CP. The  
negative edge of XTR enables the count-down to begin with  
the next positive edge of CP. When the count reaches zero,  
Q, normally low, is brought HIGH for a single period of CP.  
Q/2 toggles state on the positive edge of Q. Taking XTR  
HIGH before the counters reach zero, stops the count-down  
from the point where it was held. Data cannot be reloaded  
into the counter until a count of zero is reached. See Figure  
3.  
When XTR is HIGH, the data in the data latches is loaded  
into the counter upon the positive edge of CP. The negative  
edge of XTR enables the count-down to begin with the next  
positive edge of CP. When the count reaches zero, Q, nor-  
mally LOW, is brought HIGH for a single period of CP and  
Q/2 is toggled. The same clock edge that brings Q HIGH,  
also loads the data in the data latches into the counter. The  
counter will start to count on the next positive edge of CP.  
This mode will run continuously after an initial XTR until  
stopped by MR. Taking XTR HIGH at any time causes the  
data in the data latches to be loaded into the counter and Q  
output to be cleared with the next positive edge of CP. See  
Figure 5.  
MODE 5: Interval Timer, Inverted Pulse Output with  
Count Hold  
The operation is exactly the same as Mode 4 except that Q  
is normally HIGH and goes LOW for a single period of CP.  
Q/2 toggles on the negative-edge of Q. See Figure 3.  
Block Diagram  
TL/F/9547–4  
3

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