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74F525

更新时间： 2024-01-01 07:28:13
品牌 Logo 应用领域
美国国家半导体 - NSC 计数器
页数 文件大小 规格书
10页 174K
描述
Programmable Counter

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74F525 技术参数

生命周期：Obsolete零件包装代码：DIP
包装说明：DIP,针数：28
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.83其他特性：PROGRAMMABLE 16 BIT DOWN COUNTER; 8 MODES OF OPERATION; DIVIDE BY N AND N/2 OUTPUTS AVAILABLE
计数方向：DOWN系列：F/FAST
JESD-30 代码：R-PDIP-T28负载/预设输入：YES
逻辑集成电路类型：DIVIDE BY N COUNTER工作模式：ASYNCHRONOUS
功能数量：1端子数量：28
最高工作温度：70 °C最低工作温度：
封装主体材料：PLASTIC/EPOXY封装代码：DIP
封装形状：RECTANGULAR封装形式：IN-LINE
传播延迟（tpd）：22 ns认证状态：Not Qualified
最大供电电压 (Vsup)：5.25 V最小供电电压 (Vsup)：4.75 V
标称供电电压 (Vsup)：5 V表面贴装：NO
技术：TTL温度等级：COMMERCIAL
端子形式：THROUGH-HOLE端子位置：DUAL
触发器类型：POSITIVE EDGE最小 fmax：60 MHz

74F525 数据手册

 浏览型号74F525的Datasheet PDF文件第1页浏览型号74F525的Datasheet PDF文件第3页浏览型号74F525的Datasheet PDF文件第4页浏览型号74F525的Datasheet PDF文件第5页浏览型号74F525的Datasheet PDF文件第6页浏览型号74F525的Datasheet PDF文件第7页 
Logic Symbol  
TL/F/9547–1  
Unit Loading/Fan Out  
74F  
Pin Names  
Description  
U.L.  
Input I /I  
IH IL  
HIGH/LOW  
Output I /I  
OH OL  
b
Q
Ouput (Primarily indicates when  
the counter has reached zero)  
Output (Divides Q by 2)  
Status Inputs  
50/33.3  
1 mA/20 mA  
b
Q/2  
50/33.3  
1.0/1.0  
1.0/1.0  
1.0/2.0  
1.0/1.0  
1.0/1.0  
1.0/2.0  
1.0/1.0  
1 mA/20 mA  
b
20 mA/ 0.6 mA  
b
20 mA/ 0.6 mA  
b
20 mA/ 1.2 mA  
b
20 mA/ 0.6 mA  
b
20 mA/ 0.6 mA  
b
20 mA/ 1.2 mA  
M –M  
0
2
MR  
CP  
Master Reset  
Clock Pulse  
D –D  
0
Data Inputs  
15  
WE  
Write Enable Input  
External Trigger Input  
Crystal Output  
XTR  
XTAL  
b
20 mA/ 0.6 mA  
Functional Description  
The multi-function aspect of the device consists of eight  
different modes of operation. An explanation of the opera-  
tion of the device in each of the modes follows. However,  
there is one operation that is independent of the selected  
mode: the loading of data. Data is latched into a set of data  
latches when WE is brought from a LOW to a HIGH state.  
The latches are transparent when WE is held LOW.  
Q, normally LOW, is brought HIGH and Q/2 toggles state.  
Taking XTR HIGH at any time enables the data in the data  
latches to be loaded into the counter on the rising edge of  
CP and clears Q. See Figure 1.  
MODE 1: Interval Timer with Inverted Level Output  
The operation is exactly the same as in Mode 0 except that  
Q is normally HIGH and goes LOW when the count reaches  
zero. Q/2 toggles on the negative-edge of Q. See Figure 1.  
Operation Notes:  
1. Device should be reset before operation.  
2. The XTR input acts as a select line for the clock.  
3. With XTR low, the clock goes into the counter.  
4. With XTR high, the clock loads the counter.  
MODE 2: Interval Timer with Pulse Output  
While XTR is HIGH, the data in the data latches is loaded  
into the counter upon the next positive edge of CP. The  
negative edge of XTR enables the count-down to begin with  
the next positive edge of CP. When the count reaches zero,  
Q, normally LOW, is brought HIGH for a single period of CP.  
Q/2 toggles state on the positive edge of Q. Taking XTR  
HIGH at any time causes the data in the data latches to be  
loaded into the counter on the rising edge of CP and clears  
Q. See Figure 2.  
5. In mode 4 and 5, during counting, the counter cannot be  
reloaded. XTR high freezes the count.  
6. Mode 7 is the only auto-reload mode, all other modes  
require and XTR pulse to begin.  
7. Loading 0 into the latches idles the device.  
MODE 0: Interval Timer with Level Output  
MODE 3: Interval Timer with Inverted Pulse Output  
While XTR is HIGH, the data in the data latches is loaded  
into the counter upon the next positive edge of CP. The  
negative edge of XTR enables the count-down to begin with  
the next positive edge of CP. When the count reaches zero,  
The operation is exactly the same as in Mode 2 except that  
Q is normally HIGH and goes LOW for a single period of CP.  
Q/2 toggles on the negative edge of Q. See Figure 2.  
2
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