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74F322 PDF预览

74F322

更新时间: 2024-01-03 07:38:14
品牌 Logo 应用领域
恩智浦 - NXP /
页数 文件大小 规格书
9页 82K
描述
8-bit serial/parallel register with sign extend 3-State

74F322 技术参数

生命周期:Obsolete零件包装代码:SOIC
包装说明:SOP,针数:20
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.84其他特性:COMMON I/O PINS; MUXED SERIAL INPUTS; SIGN EXTEND FUNCTION; TOTEMPOLE SERIAL SHIFT RIGHT OUTPUT
计数方向:RIGHT系列:F/FAST
JESD-30 代码:R-PDSO-G20长度:12.8 mm
逻辑集成电路类型:PARALLEL IN PARALLEL OUT位数:8
功能数量:1端子数量:20
最高工作温度:70 °C最低工作温度:
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
传播延迟(tpd):9 ns认证状态:Not Qualified
座面最大高度:2.65 mm最大供电电压 (Vsup):5.25 V
最小供电电压 (Vsup):4.75 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:TTL
温度等级:COMMERCIAL端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
触发器类型:POSITIVE EDGE宽度:7.5 mm
最小 fmax:90 MHzBase Number Matches:1

74F322 数据手册

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Philips Semiconductors  
Product specification  
8-bit serial/parallel register with sign extend (3-State)  
74F322  
FEATURES  
PIN CONFIGURATION  
Multiplexed parallel I/O ports  
RE  
S/P  
D0  
1
2
3
4
5
20  
19  
Separate serial input and output  
Sign extend function  
V
CC  
S
18 SE  
17 D1  
3-State outputs for bus applications  
Direct Overriding Clear  
I/O0  
I/O2  
I/O4  
I/O1  
16  
15  
14  
13  
I/O3  
I/O5  
I/O7  
6
7
8
9
DESCRIPTION  
The 74F322 is an 8-bit shift register with provision for either serial or  
parallel loading and with 3-State parallel outputs plus a bi-state  
serial output. Parallel data inputs and outputs are multiplexed to  
minimize pin count. State changes are initiated by the rising edge of  
the clock. Four synchronous modes of operation are possible: hold  
(store), shift right with serial entry, shift right with sign extend, and  
parallel load. An asynchronous Master Reset (MR) input overrides  
clocked operation and clears the registers.  
I/O6  
OE  
MR  
12 Q7  
11 CP  
GND 10  
SF00874  
TYPICAL  
SUPPLY CURRENT  
(TOTAL)  
The 74F322 contains eight D-type edge triggered flip-flops and the  
interstage gating required to perform right shift and the intrastage  
gating necessary for hold and synchronous parallel load operations.  
A Low signal on RE enables shifting or parallel loading, while a High  
signal enables the hold mode. A High signal on S/P enables shift  
right, while a Low signal disables the 3-State output buffers and  
enables parallel loading. In the shift right mode a High signal on SE  
enables serial entry from either D0 or D1, as determined by the S  
input. A Low signal on SE enables shift right, but Q7 reloads its  
contents, thus performing the sign extend function. A High signal on  
OE disables the 3-State output buffers, regardless of the other  
control inputs. In this condition the shifting and loading operations  
can still be performed.  
TYPE  
TYPICAL f  
MAX  
74F322  
125MHz  
60mA  
ORDERING INFORMATION  
ORDER CODE  
DESCRIPTION  
COMMERCIAL RANGE  
= 5V ±10%, T = 0°C to +70°C  
V
CC  
amb  
20-pin plastic DIP  
20-pin plastic SOL  
N74F322N  
N74F322D  
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE  
74F(U.L.)  
LOAD VALUE  
HIGH/LOW  
PINS  
DESCRIPTION  
HIGH/LOW  
1.0/1.0  
1.0/2.0  
1.0/3.0  
1.0/1.0  
1.0/1.0  
1.0/1.0  
1.0/1.0  
1.0/1.0  
50/33  
D0, D1  
S
Serial data inputs  
20µA/0.6mA  
20µA/1.2mA  
20µA/1.8mA  
20µA/0.6mA  
20µA/0.6mA  
20µA/0.6mA  
20µA/0.6mA  
20µA/0.6mA  
1.0mA/20mA  
70µA/0.6mA  
3.0mA/24mA  
Serial data select input  
Sign Extend input  
SE  
CP  
Clock Pulse input (Active rising edge)  
Serial (High) or Parallel (Low) mode control input  
Register Enable input (Active Low)  
Asynchronous Master Reset input (Active Low)  
Output Enable input (Active Low)  
Bi-state serial output  
S/P  
RE  
MR  
OE  
Q7  
Multiplexed parallel data inputs or  
3-State parallel outputs  
3.5/1.0  
150/40  
I/On  
NOTE: One (1.0) FAST Unit Load (U.L.) is defined as: 20µA in the High State and 0.6mA in the Low state.  
1
1988 Apr 22  
853-0366 93020  

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