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74F169D-T PDF预览

74F169D-T

更新时间： 2024-01-12 09:44:01
品牌 Logo 应用领域
恩智浦 - NXP 计数器
页数 文件大小 规格书
12页 117K
描述
IC F/FAST SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT BIDIRECTIONAL BINARY COUNTER, PDSO16, PLASTIC, SOT-162-1, SO-16, Counter

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74F169D-T 技术参数

生命周期：Obsolete零件包装代码：SOIC
包装说明：0.300 INCH, PLASTIC, SOIC-16针数：16
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.68Is Samacsys：N
计数方向：BIDIRECTIONAL系列：F/FAST
JESD-30 代码：R-PDSO-G16长度：10.11 mm
负载/预设输入：YES逻辑集成电路类型：BINARY COUNTER
工作模式：SYNCHRONOUS位数：4
功能数量：1端子数量：16
最高工作温度：70 °C最低工作温度：
封装主体材料：PLASTIC/EPOXY封装代码：SOP
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
传播延迟（tpd）：13 ns座面最大高度：2.108 mm
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：4.5 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：TTL温度等级：COMMERCIAL
端子形式：GULL WING端子节距：1.27 mm
端子位置：DUAL触发器类型：POSITIVE EDGE
宽度：5.3 mm最小 fmax：70 MHz
Base Number Matches：1

74F169D-T 数据手册

 浏览型号74F169D-T的Datasheet PDF文件第1页浏览型号74F169D-T的Datasheet PDF文件第2页浏览型号74F169D-T的Datasheet PDF文件第4页浏览型号74F169D-T的Datasheet PDF文件第5页浏览型号74F169D-T的Datasheet PDF文件第6页浏览型号74F169D-T的Datasheet PDF文件第7页 
Philips Semiconductors  
Product specification  
4-bit up/down binary synchronous counter  
74F169  
LOGIC SYMBOL  
LOGIC SYMBOL (IEEE/IEC)  
CTR DIV 16  
3
4
5
6
9
M1 [LOAD]  
M2 [COUNT]  
D
D
D
D
3
1
0
1
2
9
PE  
M3 [UP]  
M4 [DOWN]  
10  
1
2
7
U/D  
CP  
15  
3, 5 CT=15  
4, 5 CT=0  
G5  
G6  
TC  
15  
7
2
CEP  
CET  
2, 3, 5, 6+/C7  
2, 4, 5, 6–  
10  
Q
Q
Q
Q
3
0
1
2
3
14  
13  
12  
1, 7D  
[1]  
[2]  
[4]  
[8]  
14  
13  
12  
11  
4
5
6
V
= Pin 16  
11  
CC  
GND = Pin 8  
SF00786  
SF00787  
FUNCTIONAL DESCRIPTION  
The 74F169 uses edge-triggered J-K-type flip-flops and have no  
constraints on changing the control or data input signals in either  
state of the clock. The only requirement is that the various inputs  
attain the desired state at least a setup time before the rising edge  
of the clock and remain valid for the recommended hold time  
thereafter. The parallel load operation takes precedence over the  
other operations, as indicated in the Mode Select Table. When PE is  
when a counter reaches zero in the Count Down mode or reaches  
15 in the Count Up mode. The TC output state is not a function of  
the Count Enable Parallel (CEP) input level. Since the TC signal is  
derived by decoding the flip-flop states, there exists the possibility of  
decoding spikes on TC. For this reason the use of TC as a clock  
signal is not recommended (see logic equations below).  
1) Count Enable = CEP CET PE  
Low, the data on the D - D inputs enter the flip-flops on the next  
0
3
rising edge of the Clock. In order for counting to occur, both CEP  
and CET must be Low and PE must be High; the U/D input  
determines the direction of counting. The Terminal Count (TC)  
output is normally High and goes Low, provided that CET is Low,  
2) Up: TC = Q Q (U/D) CET  
0
3
3) Down: TC = Q Q Q Q (U/D) CET  
0
1
2
3
MODE SELECT — FUNCTION TABLE  
INPUTS  
OUTPUTS  
OPERATING MODE  
Parallel load (Dn→Qn)  
CP  
U/D  
CEP  
CET  
PE  
D
Q
TC  
n
n
↑
↑
X
X
X
X
X
X
l
l
L
(1)  
(1)  
X
X
H
h
l
l
l
l
l
h
h
X
X
Count Up  
(1)  
(1)  
Count Up (increment)  
Count Down (decrement)  
Hold (do nothing)  
↑
↑
Count Down  
X
X
h
X
X
h
h
X
X
q
n
(1)  
H
↑
↑
X
q
n
H = High voltage level steady state  
h
L
l
= High voltage level one setup time prior to the Low-to-High clock transition  
= Low voltage level steady state  
= Low voltage level one setup time prior to the Low-to-High clock transition  
q
= Lower case letters indicate the state of the referenced output prior to the Low-to-High clock transition  
X = Don’t care  
= Low-to-High clock transition  
↑
(1)= The TC is Low when CET is Low and the counter is at Terminal Count.  
Terminal Count Up is (HHHH) and Terminal Count Down is (LLLL).  
3
1996 Jan 05  
1234567...12

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