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74F174 PDF预览

74F174

更新时间: 2024-01-26 00:00:50
品牌 Logo 应用领域
美国国家半导体 - NSC 触发器
页数 文件大小 规格书
8页 168K
描述
Hex D Flip-Flop with Master Reset

74F174 技术参数

生命周期:Obsolete零件包装代码:SOIC
包装说明:SOP,针数:16
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.65系列:F/FAST
JESD-30 代码:R-PDSO-G16长度:10.3 mm
逻辑集成电路类型:D FLIP-FLOP位数:6
功能数量:1端子数量:16
最高工作温度:70 °C最低工作温度:
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE传播延迟(tpd):11 ns
认证状态:Not Qualified座面最大高度:2.65 mm
最大供电电压 (Vsup):5.25 V最小供电电压 (Vsup):4.75 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:TTL温度等级:COMMERCIAL
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL触发器类型:POSITIVE EDGE
宽度:7.5 mm最小 fmax:140 MHz
Base Number Matches:1

74F174 数据手册

 浏览型号74F174的Datasheet PDF文件第2页浏览型号74F174的Datasheet PDF文件第3页浏览型号74F174的Datasheet PDF文件第4页浏览型号74F174的Datasheet PDF文件第5页浏览型号74F174的Datasheet PDF文件第6页浏览型号74F174的Datasheet PDF文件第7页 
November 1994  
54F/74F174 Hex D Flip-Flop with Master Reset  
General Description  
Features  
Y
Edge-triggered D-type inputs  
The ’F174 is a high-speed hex D flip-flop. The device is  
used primarily as a 6-bit edge-triggered storage register.  
The information on the D inputs is transferred to storage  
during the LOW-to-HIGH clock transition. The device has a  
Master Reset to simultaneously clear all flip-flops.  
Y
Buffered positive edge-triggered clock  
Y
Asynchronous common reset  
Y
Guaranteed 4000V minimum ESD protection  
Package  
Commercial  
74F174PC  
Military  
Package Description  
Number  
N16E  
J16A  
16-Lead (0.300 Wide) Molded Dual-In-Line  
×
54F174DM (Note 2)  
16-Lead Ceramic Dual-In-Line  
74F174SC (Note 1)  
74F174SJ (Note 1)  
M16A  
M16D  
W16A  
E20A  
16-Lead (0.150 Wide) Molded Small Outline, JEDEC  
×
16-Lead (0.300 Wide) Molded Small Outline, EIAJ  
×
54F174FM (Note 2)  
54F174LM (Note 2)  
16-Lead Cerpack  
20-Lead Ceramic Leadless Chip Carrier, Type C  
e
Note 1: Devices also available in 13 reel. Use Suffix  
SCX and SJX.  
×
Note 2: Military grade device with environmental and burn-in processing. Use suffix  
e
DMQB, FMQB and LMQB.  
Logic Symbols  
Connection Diagrams  
Pin Assignment for  
DIP, SOIC and Flatpak  
Pin Assignment  
for LCC  
TL/F/9489–3  
TL/F/9489–1  
TL/F/9489–2  
IEEE/IEC  
TL/F/9489–5  
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.  
C
1995 National Semiconductor Corporation  
TL/F/9489  
RRD-B30M75/Printed in U. S. A.  

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