Datasheet > 74AUP1T02GW

74AUP1T02GW

更新时间： 2023-09-03 20:37:32

品牌	Logo	应用领域
安世 - NEXPERIA		/
页数	文件大小	规格书
13页	231K
描述
Low-power 2-input NOR gate with voltage-level translatorProduction

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74AUP1T02GW 数据手册

Nexperia

74AUP1T02

Low-power 2-input NOR gate with voltage-level translator

4. Marking

Table 2. Marking

Type number

Marking code[1]

74AUP1T02GW

74AUP1T02GX

[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.

5. Functional diagram

≥1

aaa-027762

aaa-027763

aaa-027764

Fig. 1. Logic symbol

Fig. 2. IEC logic symbol

Fig. 3. Logic diagram

6. Pinning information

6.1. Pinning

GX package

SOT1226-3 (X2SON5)

GW package

SOT353-1 (TSSOP5)

GND

aaa-035737

Transparent top view

aaa-035731

6.2. Pin description

Table 3. Pin description

Symbol

Description

data input

GND

ground (0 V)

data output

supply voltage

V_CC

74AUP1T02

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4 — 21 July 2023

2 / 13

123 4 5 6 7...13

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