Datasheet > 74AUP1T00GW

74AUP1T00GW

更新时间： 2022-02-26 12:27:21

品牌	Logo	应用领域
安世 - NEXPERIA		/
页数	文件大小	规格书
15页	202K
描述
Low-power 2-input NAND gate with voltage-level translator

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74AUP1T00GW 数据手册

Nexperia

74AUP1T00

Low-power 2-input NAND gate with voltage-level translator

11 Dynamic characteristics

Table 8.ꢀDynamic characteristics

Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 7.

Symbol Parameter

Conditions

25 °C

-40 °C to +125 °C

Unit

Min

Typ ^[1]

Max

Min

Max

(85 °C) (125 °C)

V_CC= 2.3 V to 2.7 V; V_I= 1.65 V to 1.95 V

[2]

t_pd

propagation

delay

A, B to Y; see Figure 6

C_L= 5 pF

1.9

2.4

2.8

3.8

3.4

3.9

4.4

5.6

5.3

6.0

6.6

8.0

0.5

1.0

1.5

6.8

7.9

7.5

8.7

C_L= 10 pF

C_L= 15 pF

8.7

9.6

C_L= 30 pF

10.8

11.9

V_CC= 2.3 V to 2.7 V; V_I= 2.3 V to 2.7 V

t_pd

propagation

delay

A, B to Y; see Figure 6

C_L= 5 pF

1.4

1.9

2.3

3.4

3.2

3.8

4.3

5.5

5.3

6.0

6.6

8.0

0.5

1.0

1.5

6.0

7.1

6.6

7.9

C_L= 10 pF

C_L= 15 pF

7.9

8.7

C_L= 30 pF

10.0

11.0

V_CC= 2.3 V to 2.7 V; V_I= 3.0 V to 3.6 V

t_pd

propagation

delay

A, B to Y; see Figure 6

C_L= 5 pF

1.2

1.6

2.1

3.1

3.0

3.5

4.0

5.2

4.8

5.5

6.1

7.5

0.5

1.0

1.5

5.5

6.5

7.4

9.5

6.1

7.2

C_L= 10 pF

C_L= 15 pF

8.2

C_L= 30 pF

10.5

V_CC= 3.0 V to 3.6 V; V_I= 1.65 V to 1.95 V

t_pd

propagation

delay

A, B to Y; see Figure 6

C_L= 5 pF

1.9

2.3

2.6

3.4

2.8

3.4

3.8

5.0

3.9

4.7

5.3

6.8

0.5

1.0

1.5

8.0

8.5

9.1

9.8

9.0

9.4

C_L= 10 pF

C_L= 15 pF

10.1

10.8

C_L= 30 pF

V_CC= 3.0 V to 3.6 V; V_I= 2.3 V to 2.7 V

t_pd

propagation

delay

A, B to Y; see Figure 6

C_L= 5 pF

1.4

1.9

2.3

3.3

2.7

3.3

3.7

4.9

4.2

4.9

5.5

6.8

0.5

1.0

1.5

5.3

6.1

6.8

8.5

5.9

6.8

7.5

9.4

C_L= 10 pF

C_L= 15 pF

C_L= 30 pF

74AUP1T00

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Product data sheet

Rev. 1 — 23 November 2017

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