Datasheet > 74AUP1G17GM,132

74AUP1G17GM,132

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74AUP1G17GM,132 数据手册

74AUP1G17

Low-power Schmitt trigger

Rev. 7 — 16 July 2012

Product data sheet

1. General description

The 74AUP1G17 provides the single Schmitt trigger buffer. It is capable of transforming

slowly changing input signals into sharply defined, jitter-free output signals.

This device ensures a very low static and dynamic power consumption across the entire

V_CCrange from 0.8 V to 3.6 V.

This device is fully specified for partial Power-down applications using I_OFF

The I_OFFcircuitry disables the output, preventing the damaging backflow current through

the device when it is powered down.

The inputs switch at different points for positive and negative-going signals. The difference

between the positive voltage V_T+and the negative voltage V_Tis defined as the input

hysteresis voltage V_H.

2. Features and benefits

 Wide supply voltage range from 0.8 V to 3.6 V

 High noise immunity

 ESD protection:

 HBM JESD22-A114F Class 3A exceeds 5000 V

 MM JESD22-A115-A exceeds 200 V

 CDM JESD22-C101E exceeds 1000 V

 Low static power consumption; I_CC= 0.9 A (maximum)

 Latch-up performance exceeds 100 mA per JESD 78 Class II

 Inputs accept voltages up to 3.6 V

 Low noise overshoot and undershoot < 10 % of V_CC

 I_OFFcircuitry provides partial Power-down mode operation

 Multiple package options

 Specified from 40 C to +85 C and 40 C to +125 C

12 3 4 5 6 7...24

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