74AUP1G17
Low-power Schmitt trigger
Rev. 14 — 18 July 2023
Product data sheet
1. General description
The 74AUP1G17 is a single buffer with Schmitt-trigger input. This device ensures very low static
and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is
fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output,
preventing the potentially damaging backflow current through the device when it is powered down.
2. Features and benefits
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Wide supply voltage range from 0.8 V to 3.6 V
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CMOS low power dissipation
High noise immunity
Overvoltage tolerant inputs to 3.6 V
Low noise overshoot and undershoot < 10 % of VCC
IOFF circuitry provides partial Power-down mode operation
Latch-up performance exceeds 100 mA per JESD 78 Class II Level B
Low static power consumption; ICC = 0.9 μA (maximum)
Complies with JEDEC standards:
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JESD8-12 (0.8 V to 1.3 V)
JESD8-11 (0.9 V to 1.65 V)
JESD8-7 (1.2 V to 1.95 V)
JESD8-5 (1.8 V to 2.7 V)
JESD8C (2.7 V to 3.6 V)
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ESD protection:
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HBM: ANSI/ESDA/JEDEC JS-001 class 3A exceeds 5000 V
CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
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Multiple package options
Specified from -40 ° C to +85 ° C and -40 ° C to +125 ° C