Datasheet > 74AHCT1G79-Q100

74AHCT1G79-Q100

更新时间： 2022-02-26 11:29:10

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安世 - NEXPERIA		/
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14页	721K
描述
Single D-type flip-flop; positive-edge trigger

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74AHCT1G79-Q100 数据手册

74AHC1G79-Q100; 74AHCT1G79-Q100

Nexperia

Single D-type flip-flop; positive-edge trigger

Table 8.

Dynamic characteristics …continued

GND = 0 V; t_r= t_f=  3.0 ns. For test circuit, see Figure 6. For waveforms, see Figure 5.

Symbol Parameter Conditions

25 C

40 C to +85 C 40 C to +125 C Unit

Min Typ Max

Min

3.0

Max

Min

4.0

Max

t_W

pulse width clock HIGH or LOW

3.0

f_max

maximum

frequency

MHz

[4]

C_PD

power

per buffer;

dissipation

C_L= 50 pF; f = 1 MHz;

capacitance V_I= GND to V_CC

[1] t_pdis the same as t_PLHand t_PHL

[2] Typical values are measured at V_CC= 3.3 V.

[3] Typical values are measured at V_CC= 5.0 V.

[4] C_PDis used to determine the dynamic power dissipation P_D(W).

P_D= C_PD V_CC² f_i+  (C_L V_CC² f_o) where:

f_i= input frequency in MHz;

f_o= output frequency in MHz;

C_L= output load capacitance in pF;

V_CC= supply voltage in Volts.

12. Waveforms

'ꢆLQSXW

*1'

ꢁꢅI

PD[

&3ꢆLQSXW

4ꢆRXWSXW

*1'

3/+

3+/

PQDꢆꢀꢅ

Measurement points are given in Table 9.

V_OLand V_OHare typical output voltage levels that occur with the output.

Fig 5. Clock (CP) to output (Q) propagation delay times, clock pulse width, D to set-up times, the CP to D hold

times and maximum clock pulse frequency

74AHC_AHCT1G79_Q100

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Product data sheet

Rev. 2 — 23 September 2014

7 of 14

1...4 5 678 9 10...14

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