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74ACTQ533CW PDF预览

74ACTQ533CW

更新时间: 2024-02-21 12:09:31
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 驱动逻辑集成电路
页数 文件大小 规格书
8页 92K
描述
Bus Driver, ACT Series, 1-Func, 8-Bit, Inverted Output, CMOS, DIE

74ACTQ533CW 技术参数

生命周期:Obsolete零件包装代码:DIE
包装说明:DIE,针数:20
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.74系列:ACT
JESD-30 代码:R-XUUC-N20逻辑集成电路类型:BUS DRIVER
位数:8功能数量:1
端口数量:2端子数量:20
输出特性:3-STATE输出极性:INVERTED
封装主体材料:UNSPECIFIED封装代码:DIE
封装形状:RECTANGULAR封装形式:UNCASED CHIP
传播延迟(tpd):9 ns认证状态:Not Qualified
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS端子形式:NO LEAD
端子位置:UPPERBase Number Matches:1

74ACTQ533CW 数据手册

 浏览型号74ACTQ533CW的Datasheet PDF文件第2页浏览型号74ACTQ533CW的Datasheet PDF文件第3页浏览型号74ACTQ533CW的Datasheet PDF文件第4页浏览型号74ACTQ533CW的Datasheet PDF文件第5页浏览型号74ACTQ533CW的Datasheet PDF文件第6页浏览型号74ACTQ533CW的Datasheet PDF文件第7页 
January 1990  
Revised November 1999  
74ACTQ533  
Quiet Series Octal Transparent Latch  
with 3-STATE Outputs  
General Description  
Features  
ICC and IOZ reduced by 50%  
The ACTQ533 consists of eight latches with 3-STATE out-  
puts for bus organized system applications. The flip-flops  
appear transparent to the data when Latch Enable (LE) is  
HIGH. When LE is LOW, the data satisfying the input tim-  
ing requirements is latched. Data appears on the bus when  
the Output Enable (OE) is LOW. When OE is HIGH, the  
bus output is in the high impedance state.  
Guaranteed simultaneous switching noise level and  
dynamic threshold performance  
Guaranteed pin-to-pin skew AC performance  
Improved latch up immunity  
Eight latches in a single package  
The ACTQ533 utilizes Fairchild Quiet Series technology  
to guarantee quiet output switching and improve dynamic  
threshold performance. FACT Quiet Series features GTO  
output control and undershoot corrector in addition to a  
split ground bus for superior performance.  
3-STATE outputs drive bus lines or buffer memory  
address registers  
Outputs source/sink 24 mA  
Inverted version of the ACTQ373  
4 kV minimum ESD immunity  
Ordering Code:  
Order Number Package Number  
Package Description  
74ACTQ533SC  
74ACTQ533MTC  
74ACTQ533PC  
M20B  
MTC20  
N20A  
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300Wide Body  
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300Wide  
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code  
Logic Symbols  
Connection Diagram  
IEEE/IEC  
Pin Descriptions  
Pin Names  
Description  
D0D7  
LE  
Data Inputs  
Latch Enable Input  
OE  
Output Enable Input  
3-STATE Latch Outputs  
O0O7  
FACT , FACT Quiet Series , and GTO are trademarks of Fairchild Semiconductor Corporation.  
© 1999 Fairchild Semiconductor Corporation  
DS010630  
www.fairchildsemi.com  

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