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74ACTQ541 PDF预览

74ACTQ541

更新时间: 2024-02-01 10:51:43
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 驱动器
页数 文件大小 规格书
7页 167K
描述
Quiet Series Octal Buffer/Line Driver with 3-STATE Outputs

74ACTQ541 技术参数

生命周期:Obsolete包装说明:SOP,
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.7系列:ACT
JESD-30 代码:R-PDSO-G20长度:12.8 mm
逻辑集成电路类型:BUS DRIVER位数:8
功能数量:1端口数量:2
端子数量:20最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE传播延迟(tpd):7.5 ns
认证状态:Not Qualified座面最大高度:2.65 mm
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL宽度:7.5 mm
Base Number Matches:1

74ACTQ541 数据手册

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March 1993  
Revised November 1999  
74ACTQ541  
Quiet Series Octal Buffer/Line Driver  
with 3-STATE Outputs  
General Description  
The 74ACTQ541 is an octal buffer/line driver designed to  
be employed as memory and address drivers, clock drivers  
and bus oriented transmitter/receivers.  
Features  
ICC and IOZ reduced by 50%  
Guaranteed simultaneous switching noise level and  
dynamic threshold performance  
This device is similar in function to the 74ACTQ244 while  
providing flow-through architecture (inputs on opposite side  
from outputs). This pinout arrangement makes this device  
especially useful as an output port for microprocessors,  
allowing ease of layout and greater PC board density.  
Guaranteed pin-to-pin skew AC performance  
Inputs and outputs on opposite sides of package for  
easy board layout  
Non-inverting 3-STATE outputs  
Guaranteed 4 kV minimum ESD immunity  
TTL compatible inputs  
The 74ACTQ541 utilizes FACT Quiet Series technology  
to guarantee quiet output switching and improved dynamic  
threshold performance. FACT Quiet Series features GTO  
output control and undershoot corrector in addition to split  
ground bus for superior performance.  
Outputs source/sink 24 mA  
Ordering Code:  
Order Number Package Number  
Package Description  
74ACTQ541SC  
74ACTQ541MTC  
74ACTQ541PC  
M20B  
MTC20  
N20A  
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide  
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide  
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the order code.  
Logic Symbol  
Connection Diagram  
IEEE/IEC  
Truth Table  
Pin Descriptions  
Inputs  
OE2  
Pin Name  
Pin Description  
Outputs  
OE1  
I
OE1 OE2  
I0 I7  
3-STATE Output Enable (Active-LOW)  
L
H
X
L
L
X
H
L
H
X
X
L
H
Z
Z
L
Inputs  
O1 O7  
Outputs  
H = HIGH Voltage Level  
L = LOW Voltage Level  
X = Immaterial  
Z = High Impedance  
FACT , FACT Quiet Series and GTO are trademarks of Fairchild Semiconductor Corporation.  
© 1999 Fairchild Semiconductor Corporation  
DS010932  
www.fairchildsemi.com  

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