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74ACTQ543CW PDF预览

74ACTQ543CW

更新时间： 2024-09-30 21:07:15
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 逻辑集成电路
页数 文件大小 规格书
9页 92K
描述
Registered Bus Transceiver, ACT Series, 1-Func, 8-Bit, True Output, CMOS, DIE

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74ACTQ543CW 技术参数

生命周期：Obsolete零件包装代码：DIE
包装说明：DIE,针数：24
Reach Compliance Code：unknown风险等级：5.69
系列：ACTJESD-30 代码：R-XUUC-N24
逻辑集成电路类型：REGISTERED BUS TRANSCEIVER位数：8
功能数量：1端口数量：2
端子数量：24输出特性：3-STATE
输出极性：TRUE封装主体材料：UNSPECIFIED
封装代码：DIE封装形状：RECTANGULAR
封装形式：UNCASED CHIP传播延迟（tpd）：8.5 ns
认证状态：Not Qualified最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：4.5 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：CMOS
端子形式：NO LEAD端子位置：UPPER
Base Number Matches：1

74ACTQ543CW 数据手册

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January 1990  
Revised August 2000  
74ACQ543• 74ACTQ543  
Quiet Series Octal Registered Transceiver  
with 3-STATE Outputs  
General Description  
Features  
■ Guaranteed simultaneous switching noise level and  
The ACQ/ACTQ543 is a non-inverting octal transceiver  
containing two sets of D-type registers for temporary stor-  
age of data flowing in either direction. Separate Latch  
Enable and Output Enable inputs are provided for each  
register to permit independent input and output control in  
either direction of data flow.  
dynamic threshold performance  
■ Guaranteed pin-to-pin skew AC performance  
■ 8-bit octal latched transceiver  
■ Separate controls for data flow in each direction  
■ Back-to-back registers for storage  
■ Outputs source/sink 24 mA  
The ACQ/ACTQ utilizes Fairchild Quiet Series technol-  
ogy to guarantee quiet output switching and improved  
dynamic threshold performance FACT Quiet Series fea-  
tures GTO output control and undershoot corrector in  
addition to a split ground bus for superior performance.  
■ 300 mil slim PDIP/SOIC  
Ordering Code:  
Order Number Package Number  
Package Description  
74ACQ543SC  
M24B  
N24C  
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide  
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide  
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide  
24-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150 Wide  
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide  
74ACQ543SPC  
74ACTQ543SC  
74ACTQ543QSC  
74ACTQ543SPC  
M24B  
MQA24  
N24C  
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the order code.  
Connection Diagram  
Pin Descriptions  
Pin Names  
Description  
OEAB  
OEBA  
CEAB  
CEBA  
LEAB  
LEBA  
A0–A7  
A-to-B Output Enable Input (Active LOW)  
B-to-A Output Enable Input (Active LOW)  
A-to-B Enable Input (Active LOW)  
B-to-A Enable Input (Active LOW)  
A-to-B Latch Enable Input (Active LOW)  
B-to-A Latch Enable Input (Active LOW)  
A-to-B Data Inputs or  
B-to-A 3-STATE Outputs  
B0–B7  
B-to-A Data Inputs or  
A-to-B 3-STATE Outputs  
FACT , Quiet Series , FACT Quiet Series and GTO are trademarks of Fairchild Semiconductor Corporation.  
© 2000 Fairchild Semiconductor Corporation  
DS010154  
www.fairchildsemi.com  
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