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74AC174SCT PDF预览

74AC174SCT

更新时间: 2024-01-11 03:54:19
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 触发器
页数 文件大小 规格书
9页 102K
描述
D Flip-Flop, AC Series, 1-Func, Positive Edge Triggered, 6-Bit, True Output, CMOS, PDSO16, SOIC-16

74AC174SCT 技术参数

生命周期:Contact Manufacturer包装说明:TSSOP,
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.6Is Samacsys:N
系列:ACJESD-30 代码:R-PDSO-G16
长度:5 mm逻辑集成电路类型:D FLIP-FLOP
位数:6功能数量:1
端子数量:16最高工作温度:125 °C
最低工作温度:-55 °C输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
传播延迟(tpd):14 ns座面最大高度:1.2 mm
最大供电电压 (Vsup):6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL触发器类型:POSITIVE EDGE
宽度:4.4 mm最小 fmax:100 MHz
Base Number Matches:1

74AC174SCT 数据手册

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Functional Description  
Truth Table  
The AC/ACT174 consists of six edge-triggered D-type flip-  
flops with individual D inputs and Q outputs. The Clock  
(CP) and Master Reset (MR) are common to all flip-flops.  
Each D inputs state is transferred to the corresponding flip-  
flops output following the LOW-to-HIGH Clock (CP) transi-  
tion. A LOW input to the Master Reset (MR) will force all  
outputs LOW independent of Clock or Data inputs. The AC/  
ACT174 is useful for applications where the true output  
only is required and the Clock and Master Reset are com-  
mon to all storage elements.  
Inputs  
Output  
MR  
L
CP  
D
X
H
L
Q
L
X
H
H
L
H
H
L
X
Q
H = HIGH Voltage Level  
L = LOW Voltage Level  
= LOW-to-HIGH Transition  
X = Immaterial  
Logic Diagram  
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.  
www.fairchildsemi.com  
2

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