5秒后页面跳转
捷配首页

Datasheet > 74AC163SCX
74AC163SCX PDF预览

74AC163SCX

更新时间： 2024-01-17 01:06:42
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 光电二极管输出元件逻辑集成电路触发器
页数 文件大小 规格书
11页 99K
描述
Binary Counter, AC Series, Synchronous, Positive Edge Triggered, 4-Bit, Up Direction, CMOS, PDSO16, 0.150 INCH, MS-012, SOIC-16

阅读下载

获取价格

74AC163SCX 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Contact Manufacturer零件包装代码：SOIC
包装说明：SOP,针数：16
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.6Is Samacsys：N
其他特性：TCO OUTPUT计数方向：UP
系列：ACJESD-30 代码：R-PDSO-G16
JESD-609代码：e3长度：9.9 mm
负载/预设输入：YES逻辑集成电路类型：BINARY COUNTER
工作模式：SYNCHRONOUS湿度敏感等级：1
位数：4功能数量：1
端子数量：16最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：SOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE峰值回流温度（摄氏度）：260
传播延迟（tpd）：13.5 ns认证状态：Not Qualified
座面最大高度：1.75 mm最大供电电压 (Vsup)：6 V
最小供电电压 (Vsup)：2 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：MATTE TIN
端子形式：GULL WING端子节距：1.27 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
触发器类型：POSITIVE EDGE宽度：3.9 mm
最小 fmax：95 MHzBase Number Matches：1

74AC163SCX 数据手册

 浏览型号74AC163SCX的Datasheet PDF文件第1页浏览型号74AC163SCX的Datasheet PDF文件第3页浏览型号74AC163SCX的Datasheet PDF文件第4页浏览型号74AC163SCX的Datasheet PDF文件第5页浏览型号74AC163SCX的Datasheet PDF文件第6页浏览型号74AC163SCX的Datasheet PDF文件第7页 
Logic Symbols  
Functional Description  
The AC/ACT163 counts in modulo-16 binary sequence.  
From state 15 (HHHH) it increments to state 0 (LLLL). The  
clock inputs of all flip-flops are driven in parallel through a  
clock buffer. Thus all changes of the Q outputs occur as a  
result of, and synchronous with, the LOW-to-HIGH transi-  
tion of the CP input signal. The circuits have four funda-  
mental modes of operation, in order of precedence:  
synchronous reset, parallel load, count-up and hold. Four  
control inputs—Synchronous Reset (SR), Parallel Enable  
(PE), Count Enable Parallel (CEP) and Count Enable  
Trickle (CET)—determine the mode of operation, as shown  
in the Mode Select Table. A LOW signal on SR overrides  
counting and parallel loading and allows all outputs to go  
LOW on the next rising edge of CP. A LOW signal on PE  
overrides counting and allows information on the Parallel  
Data (Pn) inputs to be loaded into the flip-flops on the next  
IEEE/IEC  
rising edge of CP. With PE and SR HIGH, CEP and CET  
permit counting when both are HIGH. Conversely, a LOW  
signal on either CEP or CET inhibits counting.  
The AC/ACT163 uses D-type edge-triggered flip-flops and  
changing the SR, PE, CEP and CET inputs when the CP is  
in either state does not cause errors, provided that the rec-  
ommended setup and hold times, with respect to the rising  
edge of CP, are observed.  
The Terminal Count (TC) output is HIGH when CET is  
HIGH and counter is in state 15. To implement synchro-  
nous multistage counters, the TC outputs can be used with  
the CEP and CET inputs in two different ways.  
Mode Select Table  
Figure 1 shows the connections for simple ripple carry, in  
which the clock period must be longer than the CP to TC  
delay of the first stage, plus the cumulative CET to TC  
delays of the intermediate stages, plus the CET to CP  
setup time of the last stage. This total delay plus setup time  
sets the upper limit on clock frequency. For faster clock  
rates, the carry lookahead connections shown in Figure 2  
are recommended. In this scheme the ripple delay through  
the intermediate stages commences with the same clock  
that causes the first stage to tick over from max to min in  
the Up mode, or min to max in the Down mode, to start its  
final cycle. Since this final cycle takes 16 clocks to com-  
plete, there is plenty of time for the ripple to progress  
through the intermediate stages. The critical timing that lim-  
its the clock period is the CP to TC delay of the first stage  
plus the CEP to CP setup time of the last stage. The TC  
output is subject to decoding spikes due to internal race  
conditions and is therefore not recommended for use as a  
clock or asynchronous reset for flip-flops, registers or  
counters.  
SR  
PE  
CET  
CEP  
Action on the Rising  
Clock Edge (  
Reset (Clear)  
Load (Pn → Qn)  
)
L
H
H
H
H
X
L
X
X
H
L
X
X
H
X
L
H
H
H
Count (Increment)  
No Change (Hold)  
No Change (Hold)  
X
H = HIGH Voltage Level  
L = LOW Voltage Level  
X = Immaterial  
Logic Equations: Count Enable = CEP • CET • PE  
TC = Q0 • Q1 • Q2 • Q3 • CET  
www.fairchildsemi.com  
2
1234567...11

下载PDF

与74AC163SCX相关器件

型号 品牌 描述 获取价格 数据表
74AC163SCX_NL FAIRCHILD 暂无描述

获取价格
74AC163SCXR FAIRCHILD 暂无描述

获取价格
74AC163SJ FAIRCHILD Synchronous Presettable Binary Counter

获取价格
74AC163SJX FAIRCHILD Synchronous Up Counter

获取价格
74AC163TTR STMICROELECTRONICS SYNCHRONOUS PRESETTABLE 4-BIT COUNTER

获取价格
74AC16470DL ETC Logic IC

获取价格

与74AC163SCX相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证