November 1988
Revised February 2000
74AC163 • 74ACT163
Synchronous Presettable Binary Counter
General Description
Features
The AC/ACT163 are high-speed synchronous modulo-16
binary counters. They are synchronously presettable for
application in programmable dividers and have two types
of Count Enable inputs plus a Terminal Count output for
versatility in forming synchronous multistage counters. The
AC/ACT163 has a Synchronous Reset input that overrides
counting and parallel loading and allows the outputs to be
simultaneously reset on the rising edge of the clock.
■ ICC reduced by 50%
■ Synchronous counting and loading
■ High-speed synchronous expansion
■ Typical count rate of 125 MHz
■ Outputs source/sink 24 mA
■ ACT163 has TTL-compatible inputs
Ordering Code:
Order Number Package Number
Package Description
74AC163SC
74AC163SJ
M16A
M16D
MTC16
N16E
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body
16-Lead Small Outline Package, (SOP), EIAJ TYPE II, 5.3mm Wide
74AC163MTC
74AC163PC
74ACT163SC
74ACT163SJ
74ACT163MTC
74ACT163PC
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body
16-Lead Small Outline Package, (SOP), EIAJ TYPE II, 5.3mm Wide
M16A
M16D
MTC16
N16E
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Connection Diagram
Pin Descriptions
Pin Names
CEP
Description
Count Enable Parallel Input
Count Enable Trickle Input
Clock Pulse Input
CET
CP
SR
Synchronous Reset Input
Parallel Data Inputs
P0–P3
PE
Parallel Enable Input
Flip-Flop Outputs
Q0–Q3
TC
Terminal Count Output
© 2000 Fairchild Semiconductor Corporation
DS009932
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