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74ABT573APW-T

更新时间： 2024-01-26 03:09:36
品牌 Logo 应用领域
飞利浦 - PHILIPS 驱动信息通信管理光电二极管逻辑集成电路
页数 文件大小 规格书
6页 67K
描述
D Latch, 1-Func, 8-Bit, PDSO20

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74ABT573APW-T 技术参数

是否Rohs认证： 符合生命周期：Transferred
包装说明：TSSOP, TSSOP20,.25Reach Compliance Code：unknown
风险等级：5.73JESD-30 代码：R-PDSO-G20
逻辑集成电路类型：D LATCH最大I（ol）：0.064 A
位数：8功能数量：1
端子数量：20最高工作温度：85 °C
最低工作温度：-40 °C输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装等效代码：TSSOP20,.25封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH包装方法：TAPE AND REEL
电源：5 VProp。Delay @ Nom-Sup：5.3 ns
认证状态：Not Qualified子类别：FF/Latches
标称供电电压 (Vsup)：5 V表面贴装：YES
温度等级：INDUSTRIAL端子形式：GULL WING
端子节距：0.635 mm端子位置：DUAL
Base Number Matches：1

74ABT573APW-T 数据手册

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Philips Semiconductors  
Product specification  
74ABT573A  
Octal D-type transparent latch (3-State)  
The 74ABT573A device is an octal transparent latch coupled to  
eight 3-State output buffers. The two sections of the device are  
controlled independently by Enable (E) and Output Enable (OE)  
control gates. The 74ABT573A is functionally identical to the  
74ABT373 but has a flow-through pinout configuration to facilitate  
PC board layout and allow easy interface with microprocessors.  
FEATURES  
• 74ABT573A is flow-through pinout version of 74ABT373  
• Inputs and outputs on opposite side of package allow easy  
interface to microprocessors  
• 3-State output buffers  
• Common output enable  
• Latch-up protection exceeds 500mA per JEDEC Std 17  
The data on the D inputs are transferred to the latch outputs when  
the Latch Enable (E) input is High. The latch remains transparent to  
the data inputs while E is High, and stores the data that is present  
one setup time before the High-to-Low enable transition.  
• ESD protection exceeds 2000 V per MIL STD 883 Method 3015  
and 200 V per Machine Model  
• Power-up 3-State  
• Power-up reset  
The 3-State output buffers are designed to drive heavily loaded  
3-State buses, MOS memories, or MOS microprocessors. The  
active-Low Output Enable (OE) controls all eight 3-State buffers  
independent of the latch operation.  
DESCRIPTION  
When OE is Low, the latched or transparent data appears at the  
outputs. When OE is High, the outputs are in the High-impedance  
”OFF” state, which means they will neither drive nor load the bus.  
The 74ABT573A high-performance BiCMOS device combines low  
static and dynamic power dissipation with high speed and high  
output drive.  
QUICK REFERENCE DATA  
CONDITIONS  
= 25°C; GND = 0V  
SYMBOL  
PARAMETER  
TYPICAL  
UNIT  
T
amb  
t
t
Propagation delay  
Dn to Qn  
2.8  
3.3  
PLH  
PHL  
C = 50pF; V = 5V  
ns  
L
CC  
C
Input capacitance  
Output capacitance  
Total supply current  
V = 0V or V  
CC  
3
6
pF  
pF  
µA  
IN  
I
C
Outputs disabled; V = 0V or V  
O CC  
OUT  
CCZ  
I
Outputs disabled; V =5.5V  
100  
CC  
ORDERING INFORMATION  
PACKAGES  
TEMPERATURE RANGE OUTSIDE NORTH AMERICA  
NORTH AMERICA  
74ABT573A N  
DWG NUMBER  
SOT146-1  
20-Pin Plastic DIP  
–40°C to +85°C  
–40°C to +85°C  
–40°C to +85°C  
–40°C to +85°C  
74ABT573A N  
74ABT573A D  
74ABT573A DB  
74ABT573A PW  
20-Pin plastic SO  
74ABT573A D  
SOT163-1  
20-Pin Plastic SSOP Type II  
20-Pin Plastic TSSOP Type I  
74ABT573A DB  
74ABT573APW DH  
SOT339-1  
SOT360-1  
PIN CONFIGURATION  
PIN DESCRIPTION  
PIN  
SYMBOL  
NUMBER  
FUNCTION  
1
OE  
Output enable input (active-Low)  
Data inputs  
OE  
D0  
1
2
3
4
5
20  
19  
18  
17  
16  
V
2, 3, 4, 5,  
6, 7, 8, 9  
CC  
D0-D7  
Q0  
19, 18, 17,  
16, 15, 14,  
13, 12  
D1  
Q1  
Q2  
Q3  
Q4  
Q5  
Q6  
Q7  
E
Q0-Q7  
Data outputs  
D2  
D3  
11  
10  
20  
E
Enable input (active-High)  
Ground (0V)  
D4  
6
7
15  
14  
13  
12  
11  
GND  
D5  
V
CC  
Positive supply voltage  
D6  
8
D7  
9
GND  
10  
SA00185  
1
1995 Sep 06  
853–1455 15703  
123456

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