74ABT541CPC PDF预览

74ABT541CPC

更新时间: 2025-09-22 19:01:55
品牌 Logo 应用领域
安森美 - ONSEMI 光电二极管
页数 文件大小 规格书
10页 111K
描述
类型:缓冲器,非反向;功能单元数:1;位数(bit):8;元器件封装:20-PDIP;

74ABT541CPC 数据手册

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September 1992  
Revised November 1999  
74ABT541  
Octal Buffer/Line Driver with 3-STATE Outputs  
General Description  
The ABT541 is an octal buffer and line driver with 3-STATE  
Features  
Non-inverting buffers  
outputs designed to be employed as  
a memory and  
Output sink capability of 64 mA, source capability of  
32 mA  
address driver, clock driver, or bus-oriented transmitter/  
receiver. The ABT541 is similar to the ABT244 with broad-  
side pinout.  
Guaranteed output skew  
Guaranteed multiple output switching specifications  
Output switching specified for both 50 pF and 250 pF  
loads  
Guaranteed simultaneous switching, noise level and  
dynamic threshold performance  
Guaranteed latchup protection  
High impedance, glitch free bus loading during entire  
power up and power down cycle  
Nondestructive hot insertion capability  
Flow-through pinout for ease of PC board layout  
Disable time less than enable time to avoid bus  
contention  
Ordering Code:  
Order Number Package Number  
Package Description  
74ABT541CSC  
74ABT541CSJ  
74ABT541CMSA  
74ABT541CMTC  
74ABT541CPC  
M20B  
M20D  
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300Wide Body  
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
MSA20  
MTC20  
N20A  
20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide  
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300Wide  
Devices also available in Tape and Reel. Specify by appending suffix “X” to the ordering code.  
Connection Diagram  
Pin Descriptions  
Pin Names  
Description  
OE1, OE2  
I0I7  
Output Enable Input (Active LOW)  
Inputs  
O0O7  
Outputs  
Truth Table  
Inputs  
Outputs  
OE1  
OE2  
I
L
H
X
L
L
X
H
L
H
X
X
L
H
Z
Z
L
H = HIGH Voltage Level  
L = LOW Voltage Level  
X = Immaterial  
Z = High Impedance  
© 1999 Fairchild Semiconductor Corporation  
DS011501  
www.fairchildsemi.com  

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