73S8009C

更新时间： 2024-02-28 09:16:01

品牌	Logo	应用领域
TERIDIAN		/
页数	文件大小	规格书
33页	351K
描述
Versatile Power Management and Smart Card Interface IC

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73S8009C 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	零件包装代码：	QFN
包装说明：	4 X 4 MM, 0.80 MM HEIGHT, LEAD FREE, QFN-20	针数：	20
Reach Compliance Code：	not_compliant	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.64
Samacsys Confidence：		Samacsys Status：	Released
Schematic Symbol：	https://componentsearchengine.com/symbol.php?partID=599351	PCB Footprint：	https://componentsearchengine.com/footprint.php?partID=599351
Samacsys PartID：	599351	Samacsys Image：	https://componentsearchengine.com/Images/9/73S8009R-IMR/F.jpg
Samacsys Thumbnail Image：	https://componentsearchengine.com/Thumbnails/1/73S8009R-IMR/F.jpg	Samacsys Pin Count：	21
Samacsys Part Category：	Integrated Circuit	Samacsys Package Category：	Other
Samacsys Footprint Name：	QFN50P400X400X90-21N	Samacsys Released Date：	2017-01-11 21:24:41
Is Samacsys：	N	其他特性：	ALSO OPERATES WITH 5 VOLT SUPPLY
模拟集成电路 - 其他类型：	ANALOG CIRCUIT	JESD-30 代码：	S-XQCC-N20
长度：	4 mm	功能数量：	1
端子数量：	20	最高工作温度：	85 °C
最低工作温度：	-40 °C	封装主体材料：	UNSPECIFIED
封装代码：	HVQCCN	封装形状：	SQUARE
封装形式：	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE	峰值回流温度（摄氏度）：	NOT SPECIFIED
认证状态：	Not Qualified	座面最大高度：	0.9 mm
最大供电电压 (Vsup)：	3.6 V	最小供电电压 (Vsup)：	2.7 V
表面贴装：	YES	温度等级：	INDUSTRIAL
端子形式：	NO LEAD	端子节距：	0.5 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	4 mm	Base Number Matches：	1

73S8009C 数据手册

DS_8009C_025

73S8009C Data Sheet

Figures

Figure 1: 73S8009C Block Diagram.........................................................................................................3

Figure 2: 73S8009C 32-Pin QFN Pinout ..................................................................................................6

Figure 3: 73S8009C 20-Pin QFN Pinout ..................................................................................................6

Figure 4: Typical 73S8009C Application Schematic ...............................................................................17

Figure 5: 73S8009C Logical Block Diagram...........................................................................................19

Figure 6: Activation Sequence...............................................................................................................21

Figure 7: Deactivation Sequence...........................................................................................................22

Figure 8: OFF Activity............................................................................................................................22

Figure 9: CS Timing Definitions..............................................................................................................23

Figure 10: I/O and I/OUC State Diagram................................................................................................24

Figure 11: I/O – I/OUC Delays - Timing Diagram....................................................................................25

Figure 12: On_Off Pin............................................................................................................................26

Figure 13: Open Drain type – OFF and RDY..........................................................................................26

Figure 14: Power Input/Output Circuit, VDD, LIN, VPC, VCC, VP...........................................................26

Figure 15: Smart Card CLK Driver Circuit ..............................................................................................27

Figure 16: Smart Card RST Driver Circuit ..............................................................................................27

Figure 17: Smart Card IO, AUX1, and AUX2 Interface Circuit.................................................................28

Figure 18: Smart Card I/OUC, AUX1UC and AUX2UC Interface Circuit..................................................28

Figure 19: General Input Circuit.............................................................................................................29

Figure 20: OFF_REQ Interface Circuit ...................................................................................................29

Figure 22: 20-Pin QFN Package Dimensions.........................................................................................30

Figure 22: 32-Pin QFN Package Dimensions.........................................................................................31

Tables

Table 1: 73S8009C Pin Definitions ..........................................................................................................7

Table 2: Absolute Maximum Device Ratings ..........................................................................................10

Table 3: Recommended Operating Conditions.......................................................................................11

Table 4: DC Smart Card Interface Requirements ...................................................................................11

Table 5: Digital Signals Characteristics ..................................................................................................14

Table 6: DC Characteristics ...................................................................................................................15

Table 7: Voltage / Temperature Fault Detection Circuits.........................................................................15

Table 8: Thermal Characteristics ...........................................................................................................15

Table 9: Order Numbers and Packaging Marks......................................................................................32

Rev. 1.4

1 2 3 456 7 8...33

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