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73S1210F-68M/F/PJ

更新时间： 2024-02-08 02:48:32
品牌 Logo 应用领域
美信 - MAXIM /
页数 文件大小 规格书
126页 1104K
描述
Power Supply Management Circuit,

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73S1210F-68M/F/PJ 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：ObsoleteReach Compliance Code：compliant
ECCN代码：EAR99HTS代码：8542.39.00.01
风险等级：5.75模拟集成电路 - 其他类型：POWER SUPPLY MANAGEMENT CIRCUIT
峰值回流温度（摄氏度）：NOT SPECIFIED处于峰值回流温度下的最长时间：NOT SPECIFIED
Base Number Matches：1

73S1210F-68M/F/PJ 数据手册

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DS_1210F_001  
73S1210F Data Sheet  
Pin Name  
Description  
PRES  
53  
34  
I
Figure 41 Smart Card presence. Active high. Note: the pin has a  
very weak pull down resistor. In noisy environments, an  
external pull down may be desired to insure against a  
false card event.  
CLK  
RST  
IO  
55  
57  
61  
60  
59  
58  
36  
38  
42  
41  
40  
39  
O
O
Figure 39 Smart Card clock signal.  
Figure 39 Smart Card reset signal.  
IO  
Figure 40 Smart Card Data IO signal.  
Figure 40 Auxiliary Smart Card IO signal (C4).  
Figure 40 Auxiliary Smart Card IO signal (C8).  
AUX1  
AUX2  
VCC  
IO  
IO  
PSO  
Smart Card VCC supply voltage output. A 0.47µF  
capacitor is required and should be located at the smart  
card connector. The capacitor should be a ceramic type  
with low ESR.  
GND  
VPC  
56  
65  
37 GND  
Smart Card Ground.  
44  
PSI  
Power supply source for main voltage converter circuit. A  
10µF and a 0.1µF capacitor are required at the VPC input.  
The 10µF capacitor should be a ceramic type with low  
ESR.  
VBUS  
VBAT  
62  
64  
PSI  
PSI  
Alternate power source input from external power supply.  
Alternate power source input, typically from two series  
cells, V > 4V.  
VP  
54  
66  
35  
1
PSO  
PSI  
Intermediate output of main converter circuit. Requires an  
external 4.7µF low ESR filter capacitor to GND.  
LIN  
Connection to 10µH inductor for internal step up  
converter. Note: inductor must be rated for 400 mA  
maximum peak current.  
ON_OFF  
63  
43  
33  
I
Figure 43 Power control pin. Connected to normally open SPST  
switch to ground. Closing switch for duration greater than  
debounce period will turn 73S1210F on. If 73S1210F is  
on, closing switch will flag the 73S1210F to go to the off  
state. Firmware will control when the power is shut down.  
OFF_REQ 52  
O
Figure 33 Digital output. If ON_OFF switch is closed (to ground) for  
debounce duration and circuit is “on,” OFF_REQ will go  
high (Request to turn OFF). This output should be  
connected to an interrupt pin to signal the CPU core that a  
request to shut down power has been initiated. The  
firmware can then perform all of its shut down  
housekeeping duties before shutting down VDD.  
TBUS(3:0)  
IO  
Trace bus signals for ICE.  
0
1
2
3
50  
46  
44  
41  
Rev. 1.4  
9
1...6789101112...126

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