73M2901CL
V.22bis Single Chip Modem
TDK Semiconductor’s 73M2901CL single chip
modem includes all the basic modem functions.
Programmable configuration options make this
device highly adaptable to a wide variety of
applications.
73M2901 however special attention should be paid
when changing an existing 73M2901 design to use
the 73M2901CL. From a hardware standpoint, the
key differences involve the User I/O pins USR10,
USR11, the $65&+ pin and the HBDEN pin. An
additional user I/O pin USR20 replaces the $65&+
pin on the 73M2901CL. This pin may remain safely
connected to TXD as long as the host software does
not reconfigure USR20 as an output (S104 bit0=0).
The 73M2901CL contains a high efficiency low
power hybrid driver. Due to this enhancement
HBDEN is no longer required. This pin is an internal
no-connect and can safely remain connected to its
previous VPD or GND. The functions of USR10 and
USR11 are related to Caller ID and Line In
Use/Parallel Pickup support.
Unlike digital logic circuitry, modem designs must
contend with precise frequency tolerances and verify
low-level analog signals, to ensure acceptable
performance. Using good analog circuit design
practices will generally result in a sound design. The
crystal oscillator should be held to a 50ppm
tolerance. The following recommendations should
be taken into consideration when starting new
designs.
LAYOUT CONSIDERATIONS
Software enhancements to the 73M2901CL are
typically achieved by the addition of new AT
commands. The device can be considered a
superset of the 73M2901. When converting a design
to the 73M2901CL it is recommended that the user
check the commands and register settings for
backward compatibility to the earlier parts*.
Good analog/digital design rules must be used to
control system noise in order to obtain high
performance in modem designs. The more digital
circuitry present in the application, the more
attention to noise control is needed.
High speed, digital devices should be locally
bypassed, and the telephone line interface and the
modem should be located next to each other near
where the telephone line connection is accessed. It
is recommended that power supplies and ground
traces should be routed separately to the analog and
digital portions on the board. Digital signals should
not be routed near low-level or high impedance
analog traces.
TELEPHONE LINE INTERFACE
Transmit levels at the line are dependent on the
interface used between the pins and the line. The
internal hybrid line drivers eliminate the need for
additional active circuitry to drive the line-coupling
transformer. The analog outputs (TXAP and TXAN)
can be connected directly to the transformer (with
the required impedance matching series resistor or
network) however some low cost transformers may
be affected by the limited amount of DC current
generated by the analog outputs (DC offset); hence
it is recommended to use a coupling capacitor with
those transformers to insure maximum performance.
The line interface circuit shown on the following
page represents the basic components and values
for interfacing the TDK 73M2901CL analog pins to
the telephone line. The values of these components
have been calculated to minimize the transmission
and reception path hybrid losses and are linked by
the following equation: R15=0.242 x R13.
The 73M2901CL should be considered a high
performance analog device. A 10µF electrolytic
capacitor in parallel with a 0.1µF Ceramic capacitor
should be placed between each VPD and VND pin
as well as between VPA and VNA. A 0.1µF ceramic
capacitor should be placed between VREF and VNA
as well as VBG and VNA. Use of ground planes and
large traces on power is recommended.
73M2901CL DESIGN COMPATIBILITY
The TDK 73M2901CL is an enhanced version of the
TDK 73M2901C and has a number of new features.
These parts are highly compatible with the earlier
* (refer to the TDK 73M2901CL User Guide for complete details)
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