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73M1903-IM/F PDF预览

73M1903-IM/F

更新时间: 2024-02-12 09:54:00
品牌 Logo 应用领域
TERIDIAN 调制解调器
页数 文件大小 规格书
46页 530K
描述
Modem Analog Front End

73M1903-IM/F 技术参数

生命周期:Transferred包装说明:ROHS COMPLIANT, MO-153AC, TSSOP-20
Reach Compliance Code:unknown风险等级:5.59
商用集成电路类型:CONSUMER CIRCUITJESD-30 代码:R-PDSO-G20
长度:6.5 mm功能数量:1
端子数量:20最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH认证状态:Not Qualified
座面最大高度:1.1 mm最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):3 V表面贴装:YES
温度等级:INDUSTRIAL端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
宽度:4.4 mmBase Number Matches:1

73M1903-IM/F 数据手册

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73M1903 Data Sheet  
DS_1903_032  
The bits transmitted on the SDOUT pin are defined as follows:  
Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0  
RX15 RX14 RX13 RX12 RX11 RX10 RX9 RX8 RX7 RX6 RX5 RX4 RX3 RX2 RX1 RX0  
If the Hardware Control bit (bit 0 of register 01h) is set to zero, the 16 bits that are received on the SDIN  
are defined as follows:  
Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0  
TX15 TX14 TX13 TX12 TX11 TX10 TX9 TX8 TX7 TX6 TX5 TX4 TX3 TX2 TX1 CTL  
In this case TX0=0 is forced.  
If the Hardware Control bit (bit 0 of register 01h) is set to one, the 16 bits that are received on the SDIN  
input are defined as follows:  
Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0  
TX15 TX14 TX13 TX12 TX11 TX10 TX9 TX8 TX7 TX6 TX5 TX4 TX3 TX2 TX1 TX0  
Bit 15 is transmitted/received first. Bits RX15:0 are the receive code word. Bits TX15:0 are the transmit  
code word. If the hardware control bit is set to one, a control frame is initiated between every pair of data  
frames. If the hardware control bit is set to zero, CTL is used by software to request a control frame. If  
CTL is high, a control frame will be initiated before the next data frame. A control frame allows the  
controller to read or write status and control to the 73M1903.  
The control word received on the SDIN pin is defined as follows:  
Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0  
R/W A6  
A5  
A4  
A3  
A2  
A1  
A0  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
The control word transmitted on the SDOUT pin is defined as follows:  
Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0  
D7 D6 D5 D4 D3 D2 D1 D0  
0
0
0
0
0
0
0
0
If the R/W bit is set to a 0, the data byte transmitted on the SDOUT pin is all zeros and the data received  
on the SDIN pin is written to the register pointed to by the received address bits; A6-A0. If the R/W bit is  
set to a 1, there is no write to any register and the data byte transmitted on the SDOUT pin is the data  
contained in the register pointed to by address bits A6-A0. Only one control frame can occur between  
any two data frames.  
Writes to unimplemented registers are ignored. Reading an unimplemented register returns a value of 0.  
The position of a control data frame is controlled by the SPOS; bit 1 of register 01h. If SPOS is set to a 0  
the control frames occur mid way between data frames, i.e., the time between data frames is equal. If  
SPOS is set to a 1, the control frame is ¼ of the way between consecutive data frames, i.e., the control  
frame is closer to the first data frame. This is illustrated in Figure 3.  
New to the 73M1903 modem AFE IC is a feature that shuts off the serial clock (SCLK) after 32 cycles of  
SCLK following the frame synch (Figure 2). This feature is unavailable in the 20 TSSOP package  
option. This mode is controlled by the SckMode pin. If this pin is left open the clock will run  
continuously. If SckMode is low the clock will be gated on for 32 clocks for each FS. The SDOUT and FS  
pins change values following a rising edge of SCLK. The SDIN pin is sampled on the falling edge of  
SCLK. Figure 4 shows the timing diagrams for the serial port.  
6
Rev. 2.0  

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