Datasheet > 73M1903-IGV

73M1903-IGV

更新时间： 2024-01-29 08:07:44

品牌	Logo	应用领域
TERIDIAN		商用集成电路
页数	文件大小	规格书
45页	447K
描述
Consumer Circuit, PQFP32, TQFP-32

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技术参数
数据手册

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73M1903-IGV 技术参数

是否Rohs认证：	不符合	生命周期：	Transferred
包装说明：	TQFP-32	Reach Compliance Code：	unknown
风险等级：	5.91	商用集成电路类型：	CONSUMER CIRCUIT
JESD-30 代码：	S-PQFP-G32	长度：	7 mm
功能数量：	1	端子数量：	32
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	TQFP
封装形状：	SQUARE	封装形式：	FLATPACK, THIN PROFILE
认证状态：	Not Qualified	座面最大高度：	1.2 mm
最大供电电压 (Vsup)：	3.6 V	最小供电电压 (Vsup)：	3 V
表面贴装：	YES	温度等级：	INDUSTRIAL
端子形式：	GULL WING	端子节距：	0.8 mm
端子位置：	QUAD	宽度：	7 mm

73M1903-IGV 数据手册

73M1903

Modem Analog Front End

DATA SHEET

SIGNAL DESCRIPTION

The TERIDIAN 73M1903 modem AFE IC is available in a 32 pin TQFP or QFN package with same pin

out. The following table describes the function of each pin. There are two pairs of power supply pins,

VPA(analog) and VPD(digital). They should be separately decoupled from the supply source in order to

isolate digital noise from the analog circuits internal to the chip. Failure to adequately isolate and

decouple these supplies will compromise device performance.

PIN NAME

TYPE PIN #

DESCRIPTION

VND

GND

PWR

1,22

Negative Digital Ground

Negative Analog Ground

Positive Digital Supply

VNA

VPD

2,25

VPA

Positive Analog Supply

VPPLL

VNPLL

Positive PLL Supply, shared with VPD

Negative PLL Ground

Master reset. When this pin is a logic 0 all registers are reset to

their default states; Weak-pulled high- default

RST

Crystal oscillator input. When providing an external clock

source, drive OSCIN.

OSCIN

OSCOUT

GPIO(0-7)

I/O

Crystal oscillator circuit output pin.

3, 4, 5, 6,

Software definable digital input/output pins.

23, 24,30,31

VREF

RXAP

RXAN

TXAP

TXAN

Reference voltage pin (Reflects Vref)

Receive analog positive input.

Receive analog negative input.

Transmit analog positive output

Transmit analog negative output

Serial interface clock. With SCLK continuous selected,

Frequency = 256*Fs ( =2.4576MHz for Fs=9.6kHz)

Serial data output (or input to the host).

Serial data input (or output from the host)

SCLK

SDOUT

SDIN

Frame synchronization. (Active Low)

Type of frame sync. Open, weak-pulled high = early (mode1);

tied low = late (mode0)

TYPE

Controls the SCLK behavior after FS. Open, weak-pulled high

= SCLK Continuous; tied low = 32 clocks per R/W cycle.

SckMode

Table 1: -32 TQFP and QFN Pin Description

Page: 5 of 45

Rev 1.4

1 2 3 456 7 8...45

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