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73K322L-IP PDF预览

73K322L-IP

更新时间： 2024-01-20 23:25:36
品牌 Logo 应用领域
东电化 - TDK 调制解调器电信集成电路电信电路光电二极管
页数 文件大小 规格书
30页 289K
描述
CCITT V.23, V.22, V.21 Single-Chip Modem

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73K322L-IP 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
包装说明：DIP, DIP22,.4Reach Compliance Code：unknown
风险等级：5.92JESD-30 代码：R-PDIP-T22
JESD-609代码：e0端子数量：22
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：DIP
封装等效代码：DIP22,.4封装形状：RECTANGULAR
封装形式：IN-LINE电源：5 V
认证状态：Not Qualified子类别：Modems
最大压摆率：10 mA标称供电电压：5 V
表面贴装：NO技术：CMOS
电信集成电路类型：MODEM温度等级：INDUSTRIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：THROUGH-HOLE
端子节距：2.54 mm端子位置：DUAL

73K322L-IP 数据手册

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73K322L  
CCITT V.23, V.22, V.21  
Single-Chip Modem  
PIN DESCRIPTION  
POWER  
NAME  
PLCC/PIN  
TYPE  
DESCRIPTION  
DIP NUMBER  
GND  
VDD  
28  
15  
I
I
System Ground.  
Power supply input, 5V ±10%. Bypass with 0.1 and 22 µF capacitors  
to GND.  
VREF  
ISET  
26  
24  
O
I
An internally generated reference voltage. Bypass with 0.1 µF  
capacitor to GND.  
Chip current reference. Sets bias current for op-amps. The chip  
current is set by connecting this pin to VDD through a 2 MΩ resistor.  
ISET should be bypassed to GND with a 0.1 µF capacitor.  
PARALLEL MICROPROCESSOR CONTROL INTERFACE  
ALE  
12  
4-11  
20  
I
I/O  
I
Address Latch Enable. The falling edge of ALE latches the address  
on AD0-AD2 and the chip select on CS.  
AD0-AD7  
CS  
Address/data bus. These bidirectional tri-state multi-plexed lines carry  
information to and from the internal registers.  
Chip select. A low on this pin during the falling edge of ALE allows a  
read cycle or a write cycle to occur. AD0-AD7 will not be driven and  
no registers will be written if CS (latched) is not active. The state of  
CS is latched on the falling edge of ALE.  
CLK  
1
O
O
Output clock. This pin is selectable under processor control to be  
either the crystal frequency (for use as a processor clock) or 16 x the  
data rate for use as a baud rate clock in DPSK modes only. The pin  
defaults to the crystal frequency on reset.  
Interrupt. This open drain output signal is used to inform the  
processor that a detect flag has occurred. The processor must then  
read the detect register to determine which detect triggered the  
interrupt. INT will stay low until the processor reads the detect register  
or does a full reset.  
INT  
17  
RD  
14  
25  
I
I
Read. A low requests a read of the 73K322L internal registers. Data  
cannot be output unless both RD and the latched CS are active or  
low.  
Reset. An active high signal on this pin will put the chip into an  
inactive state. All control register bits (CR0, CR1, Tone) will be reset.  
The output of the CLK pin will be set to the crystal frequency. An  
internal pull down resistor permits power on reset using a capacitor to  
VDD.  
RESET  
4
1234567...30

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