73K224L
V.22bis, V.22, V.21, Bell 212A, 103
Single-Chip Modem
DATA SHEET
which provides an indication of monitored modem
status conditions. TR, the tone control register,
controls the DTMF generator, answer and guard
tones and RXD output gate used in the modem
initial connect sequence. CR2 is the primary DSP
control interface and CR3 controls transmit
attenuation and receive gain adjustments. All
registers are read/write except for DR and ID,
which are read only. Register control and status
bits are identified below:
REGISTER DESCRIPTIONS
Eight 8-bit internal registers are accessible for control
and status monitoring. The registers are accessed in
read or write operations by addressing the A0, A1 and
A2 address lines in serial mode, or the AD0, AD1 and
AD2 lines in parallel mode. The address lines are
latched by ALE. Register CR0 controls the method by
which data is transferred over the phone line. CR1
controls the interface between the microprocessor and
the 73K224L internal state. DR is a detect register
REGISTER BIT SUMMARY
DATA BIT NUMBER
ADDRESS
REGISTER
AD - A0
000
D7
D6
D5
D4
D3
D2
D1
D0
CONTROL
REGISTER
0
MODULATION MODULATON
TRANSMIT
MODE
2
TRANSMIT
MODE
1
TRANSMIT
MODE
0
MODULATION
OPTION
TRANSMIT
ENABLE
ANSWER/
ORIGINATE
CR0
TYPE
1
TYPE
0
CONTROL
REGISTER
1
TRANSMIT
PATTERN
1
TRANSMIT
PATTERN
0
ENABLE
DETECT
INTERRUPT
TEST
MODE
1
TEST
MODE
0
BYPASS
SCRAMBLER
CLK
CONTROL
CR1
DR
001
010
011
100
101
101
110
RESET
UNSCR.
MARK
DETECT
SPECIAL
TONE
DETECT
CALL
PROGRESS
DETECT
DETECT
REGISTER
RECEIVE
LEVEL
PATTERN
S1 DET
RECEIVE
DATA
CARRIER
DETECT
SIGNAL
QUALITY
TONE
CONTROL
REGISTER
RXD
OUTPUT
CONTOL
TRANSMIT
GUARD
TONE
TRANSMIT
ANSWER
TONE
DTMF1/
EXTENDED
OVERSPEED
DTMF0/
GUARD/
ANSWER
TRANSMIT
DTMF
DTMF2/
4W/FDX
TR
DTMF3
16 WAY
CONTROL
REGISTER
2
SPECIAL
REGISTER
ACCESS
CALL
INITIALIZE
TRANSMIT
S1
RESET
DSP
TRAIN
INHIBIT
EQUALIZER
ENABLE
CR2
CR3
SR
0
CONTROL
REGISTER
3
RECEIVE
GAIN
BOOST
TRANSMIT
ATTEN.
3
TRANSMIT
ATTEN.
2
TRANSMIT
ATTEN.
1
TRANSMIT
ATTEN.
0
TRISTATE
TX/RXCLK
TXDALT
0
SPECIAL
REGISTER
TX BAUD
CLOCK
RX UNSCR.
DATA
TXD
SOURCE
SQ
SELECT 1
SQ
SELECT 0
0
0
0
1
ID
ID
ID
ID
ID
ID
X
X
X
REGISTER
NOTE: When a register containing reserved control
bits is written into, the reserved bits must be
programmed as 0's.
X = Undefined, mask in software
Page: 6 of 31
© 2005, 2008 TERIDIAN Semiconductor Corporation
Rev 7.1