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73K222AL PDF预览

73K222AL

更新时间: 2024-01-08 08:44:10
品牌 Logo 应用领域
东电化 - TDK 调制解调器
页数 文件大小 规格书
28页 162K
描述
V.22, V.21, Bell 212A, 103 Single-Chip Modem

73K222AL 技术参数

生命周期:Obsolete包装说明:PLASTIC, DIP-40
Reach Compliance Code:unknown风险等级:5.56
其他特性:FULL DUPLEX数据速率:1.2 Mbps
JESD-30 代码:R-PDIP-T40长度:51.943 mm
功能数量:1端子数量:40
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:DIP
封装形状:RECTANGULAR封装形式:IN-LINE
认证状态:Not Qualified座面最大高度:5.588 mm
标称供电电压:5 V表面贴装:NO
电信集成电路类型:MODEM温度等级:INDUSTRIAL
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL宽度:15.24 mm
Base Number Matches:1

73K222AL 数据手册

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73K222AL  
V.22, V.21, Bell 212A, 103  
Single-Chip Modem  
PARALLEL MICROPROCESSOR INTERFACE (continued)  
NAME  
28-PIN  
TYPE  
DESCRIPTION  
Write. A low on this informs the 73K222AL that data is available on  
AD0-AD7 for writing into an internal register. Data is latched on the  
rising edge of WR. No data is written unless both WR and the latched  
CS are low.  
WR  
13  
I
SERIAL MICROPROCESSOR INTERFACE  
A0-A2  
DATA  
-
-
I
Register Address Selection. These lines carry register addresses and  
should be valid during any read or write operation.  
I/O  
Serial Control Data. Data for a read/write operation is clocked in or out  
on the falling edge of the EXCLK pin. The direction of data flow is  
controlled by the RD pin. RD low outputs data. RD high inputs data.  
RD  
-
I
I
Read. A low on this input informs the 73K222AL that data or status  
information is being read by the processor. The falling edge of the RD  
signal will initiate a read from the addressed register. The RD signal  
must continue for eight falling edges of EXCLK in order to read all eight  
bits of the referenced register. Read data is provided LSB first. Data  
will not be output unless the RD signal is active.  
WR  
-
Write. A low on this input informs the 73K222AL that data or status  
information has been shifted in through the DATA pin and is available  
for writing to an internal register. The normal procedure for a write is to  
shift in data LSB first on the DATA pin for eight consecutive falling  
edges of EXCLK and then to pulse WR low. Data is written on the  
rising edge of WR.  
NOTE: The serial control mode is provided by tying ALE high and CS low. In this configuration AD7 becomes  
DATA and AD0, AD1 and AD2 become the address only. See timing diagrams on page 20.  
5

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