73K222AL

更新时间： 2024-01-01 23:39:27

品牌	Logo	应用领域
东电化 - TDK		调制解调器
页数	文件大小	规格书
28页	162K
描述
V.22, V.21, Bell 212A, 103 Single-Chip Modem

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73K222AL 技术参数

生命周期：	Obsolete	包装说明：	PLASTIC, DIP-40
Reach Compliance Code：	unknown	风险等级：	5.56
其他特性：	FULL DUPLEX	数据速率：	1.2 Mbps
JESD-30 代码：	R-PDIP-T40	长度：	51.943 mm
功能数量：	1	端子数量：	40
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	DIP
封装形状：	RECTANGULAR	封装形式：	IN-LINE
认证状态：	Not Qualified	座面最大高度：	5.588 mm
标称供电电压：	5 V	表面贴装：	NO
电信集成电路类型：	MODEM	温度等级：	INDUSTRIAL
端子形式：	THROUGH-HOLE	端子节距：	2.54 mm
端子位置：	DUAL	宽度：	15.24 mm
Base Number Matches：	1

73K222AL 数据手册

73K222AL

V.22, V.21, Bell 212A, 103

Single-Chip

PIN DESCRIPTION

POWER

NAME

GND

VDD

28-PIN

TYPE

DESCRIPTION

System Ground.

Power supply input, 5V ±10%. Bypass with 0.1 and 22 µF capacitors to

GND.

VREF

ISET

An internally generated reference voltage. Bypass with 0.1 µF

capacitor to ground.

Chip current reference. Sets bias current for op-amps. The chip

current is set by connecting this pin to VDD through a 2 MW resistor.

ISET should be bypassed to GND with a 0.1 µF capacitor.

PARALLEL MICROPROCESSOR INTERFACE

ALE

4-11

I/O

Address latch enable. The falling edge of ALE latches the address on

AD0-AD2 and the chip select on CS.

AD0-AD7

Address/data bus. These bidirectional tri-state multiplexed lines carry

information to and from the internal registers.

Chip select. A low on this pin during the falling edge of ALE allows a

read cycle or a write cycle to occur. AD0-AD7 will not be driven and no

registers will be written if CS (latched) is not active. The state of CS is

latched on the falling edge of ALE.

CLK

Output clock. This pin is selectable under processor control to be either

the crystal frequency (for use as a processor clock) or 16 x the data

rate for use as a baud rate clock in DPSK modes only. The pin defaults

to the crystal frequency on reset.

INT

Interrupt. This open drain output signal is used to inform the processor

that a detect flag has occurred. The processor must then read the

detect register to determine which detect triggered the interrupt. INT

will stay low until the processor reads the detect register or does a full

reset.

Read. A low requests a read of the 73K222AL internal registers. Data

cannot be output unless both RD and the latched CS are active or low.

RESET

Reset. An active high signal on this pin will put the chip into an inactive

state. All control register bits (CR0, CR1, Tone) will be reset. The

output of the CLK pin will be set to the crystal frequency. An internal

pull down resistor permits power on reset using a capacitor to VDD.

1 2 345 6 7...28

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与73K222AL相关器件

型号	品牌	描述	获取价格	数据表
73K222AL-IGT	TDK	V.22, V.21, Bell 212A, 103 Single-Chip Modem	获取价格
73K222AL-IH	TDK	V.22, V.21, Bell 212A, 103 Single-Chip Modem	获取价格
73K222AL-IH/F	TERIDIAN	Single-Chip Modem	获取价格
73K222AL-IHR/F	TERIDIAN	Single-Chip Modem	获取价格
73K222AL-IP	TDK	V.22, V.21, Bell 212A, 103 Single-Chip Modem	获取价格
73K222AU	TDK	Single-Chip Modem Modem with UART	获取价格

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