73K222AL
V.22, V.21, Bell 212A, 103
Single-Chip Modem
SERIAL COMMAND INTERFACE
2400 Hz carrier (originate mode or ALB answer mode).
The 73K222AL uses a phase locked loop coherent
demodulation technique for optimum receiver
performance.
The serial command interface allows access to the
73K222AL control and status registers via a serial
command port (22-pin version only). In this mode the
A0, A1 and A2 lines provide register addresses for
data passed through the data pin under control of the
RD and WR lines. A read operation is initiated when
the RD line is taken low. The first bit is available after
RD is brought low and the next seven cycles of
EXCLK will then transfer out seven bits of the
selected address LSB first. A write takes place by
shifting in eight bits of data LSB first for eight
consecutive cycles of EXCLK. WR is then pulsed low
and data transferred into the addressed register
occurs on the rising edge of WR. This interface
mode is also supported in the 28-pin packages. See
serial control interface pin description.
FSK MODULATOR/DEMODULATOR
The FSK modulator produces a frequency modulated
analog output signal using two discrete frequencies to
represent the binary data. In Bell 103, the standard
frequencies of 1270 and 1070 Hz (originate, mark and
space) or 2225 and 2025 Hz (answer, mark and space)
are used. V.21 mode uses 980 and 1180 Hz (originate,
mark and space), or 1650 and 1850Hz (answer, mark and
space). Demodulation involves detecting the received
frequencies and decoding them into the appropriate binary
value. The rate converter and scrambler/descrambler are
bypassed in the 103 or V.21 modes.
SPECIAL DETECT CIRCUITRY
PASSBAND FILTERS AND EQUALIZERS
High and low band filters are included to shape the
amplitude and phase response of the transmit and
receive signals and provide compromise delay
equalization and rejection of out-of-band signals in the
receive channel. Amplitude and phase equalization are
necessary to compensate for distortion of the
transmission line and to reduce intersymbol
interference in the bandlimited receive signal. The
transmit signal filtering approximates a 75% square
The special detect circuitry monitors the received
analog signal to determine status or presence of
carrier, call-progress tones, answer tone and weak
received signal (long loop condition). An
unscrambled mark request signal is also detected
when the received data out of the DPSK
demodulator before the descrambler has been high
for 165.5 ms ± 6.5 ms minimum. The appropriate
detect register bit is set when one of these conditions
changes and an interrupt is generated for all
purposes except long loop. The interrupts are
disabled (masked) when the enable interrupt bit is
set to 0.
root
of
raised
Cosine
frequency
response
characteristic.
AGC
The automatic gain control maintains a signal level at
the input to the demodulators which is constant to
within 1 dB. It corrects quickly for increases in signal
which would cause clipping and provides a total
receiver dynamic range of >45 dB.
DTMF GENERATOR
The DTMF generator will output one of 16 standard
tone pairs determined by a 4-bit binary value and TX
DTMF mode bit previously loaded into the tone
register. Tone generation is initiated when the DTMF
mode is selected using the tone register and the
transmit enable (CR0 bit D1) is changed from 0 to 1.
PARALLEL BUS INTERFACE
Four 8-bit registers are provided for control, option
select and status monitoring. These registers are
addressed with the AD0, AD1, and AD2 multiplexed
address lines (latched by ALE) and appear to a control
microprocessor as four consecutive memory locations.
Two control registers and the tone register are
read/write memory. The detect register is read only
and cannot be modified except by modem response to
monitored parameters.
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