IDT72V801/72V8211/72V821/72V831/72V841/72V851 3.3V DUAL CMOS SyncFIFOTM
DUAL 256 x 9, DUAL 512 x 9, DUAL 1K x 9, DUAL 2K x 9, DUAL 4K x 9, DUAL 8K x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
PINDESCRIPTIONS
TheIDT72V801/72V811/72V821/72V831/72V841/72V851'stwoFIFOs,
referredtoasFIFOAandFIFOB,areidenticalineveryrespect.Thefollowing
descriptiondefinestheinputandoutputsignalsforFIFOA.Thecorresponding
signal names for FIFO B are provided in parentheses.
Symbol
DA0-DA8
DB0-DB8
RSA, RSB
Name I/O
ADataInputs
BDataInputs
Reset
Description
I
I
I
9-bit data inputs to RAM array A.
9-bit data inputs to RAM array B.
When RSA (RSB) is set LOW, the associated internal read and write pointers of array A (B) are set to the first
location; FFA (FFB) and PAFA (PAFB) go HIGH, and PAEA (PAEB) and EFA (EFB) go LOW. After power-
up, a reset of both FIFOs A and B is required before an initial WRITE.
WCLKA
WCLKB
Write Clock
I
I
Data is written into the FIFO A (B) on a LOW-to-HIGH transition of WCLKA (WCLKB) when the write enable(s)
areasserted.
WENA1
WENB1
WriteEnable1
If FIFO A (B) is configured to have programmable flags, WENA1 (WENB1) is the only write enable pin that can be
used. When WENA1 (WENB1) is LOW, data A (B) is written into the FIFO on every LOW-to-HIGH transition
WCLKA (WCLKB). If the FIFO is configured to have two write enables, WENA1 (WENB1) must be LOW and
WENA2 (WENB2) must be HIGH to write data into the FIFO. Data will not be written into the FIFO if FFA (FFB) is
LOW.
WENA2/LDA
WENB2/LDB
WriteEnable2/
Load
I
FIFO A (B) is configured at reset to have either two write enables or programmable flags. If LDA (LDB) is HIGH at
reset, this pin operates as a second Write Enable. If WENA2/LDA (WENB2/LDB) is LOW at reset this pin operates
as a controltoloadandreadthe programmable flagoffsets forits respective array. Ifthe FIFOis configuredtohave
two write enables, WENA1 (WENB1) must be LOW and WENA2 (WENB2) must be HIGH to write data into FIFO
A (B). Data will not be written into FIFO A (B) if FFA (FFB) is LOW. If the FIFO is configured to have programmable
flags, LDA (LDB)is heldLOWtowrite orreadthe programmable flagoffsets.
QA0-QA8
QB0-QB8
ADataOutputs
BDataOutputs
Read Clock
O
O
I
9-bitdata outputs fromRAMarrayA.
9-bitdata outputs fromRAMarrayB.
RCLKA
RCLKB
Data is read from FIFO A (B) on a LOW-to-HIGH transition of RCLKA (RCLKB) when RENA1(RENB1) and
RENA2 (RENB2) are asserted.
RENA1
RENB1
ReadEnable1
ReadEnable2
OutputEnable
Empty Flag
I
I
When RENA1 (RENB1) and RENA2 (RENB2) are LOW, data is read from FIFO A (B) on every LOW-to-HIGH
transition of RCLKA (RCLKB). Data will not be read from Array A (B) if EFA (EFB) is LOW.
RENA2
RENB2
When RENA1 (RENB1) and RENA2 (RENB2) are LOW, data is read from the FIFO A (B) on every LOW-to-
HIGH transition of RCLKA (RCLKB). Data will not be read from array A (B) if the EFA (EFB) is LOW.
OEA
I
When OEA (OEB) is LOW, outputs DA0-DA8 (DB0-DB8) are active. If OEA (OEB) is HIGH, the OEB outputs DA0-
DA8(DB0-DB8)willbe ina high-impedance state.
EFA
EFB
O
O
O
O
When EFA (EFB) is LOW, FIFO A (B) is empty and further data reads from the output are inhibited. When EFA
(EFB) is HIGH, FIFO A (B) is not empty. EFA (EFB) is synchronized to RCLKA (RCLKB).
PAEA
PAEB
Programmable
Almost-EmptyFlag
When PAEA (PAEB) is LOW, FIFO A (B) is Almost-Empty based on the offset programmed into the appropriate
offset register. The default offset at reset is Empty+7. PAEA (PAEB) is synchronized to RCLKA (RCLKB).
PAFA
PAFB
Programmable
Almost-FullFlag
WhenPAFA (PAFB)is LOW, FIFOA(B)is Almost-Fullbasedonthe offsetprogrammedintothe appropriate offset
register. The default offset at reset is Full-7. PAFA (PAFB) is synchronized to WCLKA (WCLKB).
FFA
FFB
FullFlag
When FFA (FFB) is LOW, FIFO A (B) is full and further data writes into the input are inhibited. When FFA (FFB) is
HIGH, FIFO A (B) is not full. FFA (FFB) is synchronized to WCLKA (WCLKB).
VCC
Power
Ground
+3.3V power supply pin.
0V groundpin.
GND
3
OCTOBER22,2008
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