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72V51456L7-5BB8 PDF预览

72V51456L7-5BB8

更新时间: 2024-10-02 10:26:19
品牌 Logo 应用领域
艾迪悌 - IDT LTE
页数 文件大小 规格书
57页 554K
描述
PBGA-256, Reel

72V51456L7-5BB8 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Active零件包装代码:PBGA
包装说明:BGA,针数:256
Reach Compliance Code:not_compliantECCN代码:EAR99
HTS代码:8542.32.00.71风险等级:5.82
最长访问时间:4 ns其他特性:ALTERNATIVE MEMORY WIDTH:9-BIT AND 18-BIT
周期时间:7.5 nsJESD-30 代码:S-PBGA-B256
JESD-609代码:e0内存密度:2359296 bit
内存宽度:36湿度敏感等级:3
功能数量:1端子数量:256
字数:65536 words字数代码:64000
工作模式:SYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:64KX36
可输出:YES封装主体材料:PLASTIC/EPOXY
封装代码:BGA封装形状:SQUARE
封装形式:GRID ARRAY并行/串行:PARALLEL
峰值回流温度(摄氏度):225最大供电电压 (Vsup):3.45 V
最小供电电压 (Vsup):3.15 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn63Pb37)
端子形式:BALL端子位置:BOTTOM
处于峰值回流温度下的最长时间:NOT SPECIFIEDBase Number Matches:1

72V51456L7-5BB8 数据手册

 浏览型号72V51456L7-5BB8的Datasheet PDF文件第2页浏览型号72V51456L7-5BB8的Datasheet PDF文件第3页浏览型号72V51456L7-5BB8的Datasheet PDF文件第4页浏览型号72V51456L7-5BB8的Datasheet PDF文件第5页浏览型号72V51456L7-5BB8的Datasheet PDF文件第6页浏览型号72V51456L7-5BB8的Datasheet PDF文件第7页 
3.3VMULTI-QUEUEFLOW-CONTROLDEVICES  
(16QUEUES)36BITWIDECONFIGURATION  
589,824bits  
1,179,648bits  
2,359,296bits  
IDT72V51436  
IDT72V51446  
IDT72V51456  
Shows PAE and PAF status of 8 Queues  
Direct or polled operation of flag status bus  
Global Bus Matching - (All Queues have same Input Bus Width  
and Output Bus Width)  
User Selectable Bus Matching Options:  
– x36in to x36out  
– x18in to x36out  
– x9in to x36out  
– x36in to x18out  
– x36in to x9out  
FWFT mode of operation on read port  
Packet mode operation  
Partial Reset, clears data in single Queue  
Expansion of up to 8 multi-queue devices in parallel is available  
JTAG Functionality (Boundary Scan)  
Available in a 256-pin PBGA, 1mm pitch, 17mm x 17mm  
HIGH Performance submicron CMOS technology  
Industrial temperature range (-40°C to +85°C) is available  
FEATURES:  
Choose from among the following memory density options:  
IDT72V51436  
IDT72V51446  
IDT72V51456  
Total Available Memory = 589,824 bits  
Total Available Memory = 1,179,648 bits  
Total Available Memory = 2,359,296 bits  
Configurable from 1 to 16 Queues  
Queues may be configured at master reset from the pool of  
Total Available Memory in blocks of 256 x 36  
Independent Read and Write access per queue  
User programmable via serial port  
Default multi-queue device configurations  
IDT72V51436 : 1,024 x 36 x 16Q  
IDT72V51446 : 2,048 x 36 x 16Q  
IDT72V51456 : 4,096 x 36 x 16Q  
100% Bus Utilization, Read and Write on every clock cycle  
166 MHz High speed operation (6ns cycle time)  
3.7ns access time  
Individual, Active queue flags (OV, FF, PAE, PAF, PR)  
8 bit parallel flag status on both read and write ports  
FUNCTIONALBLOCKDIAGRAM  
MULTI-QUEUE FLOW-CONTROL DEVICE  
Q
0
1
RADEN  
ESTR  
WADEN  
FSTR  
WRADD  
RDADD  
Q
7
8
REN  
WEN  
RCLK  
WCLK  
Q2  
OE  
Q
out  
D
in  
x36  
x36  
DATA IN  
DATA OUT  
OV  
FF  
PR  
PAF  
PAE  
Q15  
PAFn  
8
PAEn/PRn  
8
5935 drw01  
IDTandtheIDTlogoareregisteredtrademarksofIntegratedDeviceTechnology,Inc  
JUNE 2003  
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES  
1
2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.  
DSC-5935/9  

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