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72V70180PF8 PDF预览

72V70180PF8

更新时间: 2024-11-27 08:36:51
品牌 Logo 应用领域
艾迪悌 - IDT 电信电信集成电路
页数 文件大小 规格书
20页 140K
描述
TQFP-64, Reel

72V70180PF8 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:TQFP
包装说明:PLASTIC, TQFP-64针数:64
Reach Compliance Code:not_compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.92
JESD-30 代码:S-PQFP-G64JESD-609代码:e0
长度:14 mm湿度敏感等级:3
功能数量:1端子数量:64
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:LQFP
封装等效代码:QFP64,.6SQ,32封装形状:SQUARE
封装形式:FLATPACK, LOW PROFILE峰值回流温度(摄氏度):240
电源:3.3 V认证状态:Not Qualified
座面最大高度:1.6 mm子类别:Other Telecom ICs
最大压摆率:0.01 mA标称供电电压:3.3 V
表面贴装:YES电信集成电路类型:DIGITAL TIME SWITCH
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn85Pb15)
端子形式:GULL WING端子节距:0.8 mm
端子位置:QUAD处于峰值回流温度下的最长时间:20
宽度:14 mmBase Number Matches:1

72V70180PF8 数据手册

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3.3 VOLT TIME SLOT INTERCHANGE  
DIGITAL SWITCH  
128 x 128  
IDT72V70180  
3.3V Power Supply  
Operating Temperature Range -40°C to +85°C  
3.3V I/O with 5V Tolerant Inputs  
FEATURES:  
128 x 128 channel non-blocking switching at 2.048 Mb/s  
Per-channel variable or constant throughput delay  
Automatic identification of ST-BUS®/GCI interfaces  
Accepts 4 serial data streams of 2.048 Mb/s  
Automatic frame offset delay measurement  
Per-stream frame delay offset programming  
Per-channel high impedance output control  
Per-channel Processor Mode  
Control interface compatible to Intel/Motorola CPUs  
Connection memory block programming  
Available in 64-pin Thin Plastic Quad Flatpack (TQFP) and  
64-pin Small Thin Quad Flatpack (STQFP)  
DESCRIPTION:  
The IDT72V70180 is a non-blocking digital switch that has a capacity of  
128x128channels at2.048Mb/s.Someofthemainfeatures are:program-  
mablestreamandchannelcontrol,ProcessorMode,inputoffsetdelayandhigh-  
impedanceoutputcontrol.  
Per-streaminputdelaycontrolis providedformanaginglarge multi-chip  
switchesthattransportbothvoicechannelandconcatenateddatachannels.In  
addition,inputstreamscanbeindividuallycalibratedforinputframeoffset.  
FUNCTIONALBLOCKDIAGRAM  
RESET  
VCC GND  
ODE  
Loopback  
RX0  
RX1  
RX2  
RX3  
TX0  
TX1  
TX2  
TX3  
Output  
MUX  
Data Memory  
Transmit  
Serial Data  
Streams  
Receive  
Serial Data  
Streams  
Connection  
Memory  
Internal  
Registers  
Timing Unit  
Microprocessor Interface  
DS/  
RD  
F0i  
DTA  
D8-D15/  
CLK  
FE  
IC  
AS/ IM  
ALE  
R/W/ A0-A7  
WR  
CS  
AD0-AD7  
5716 drw01  
IDTandtheIDTlogoareregisteredtrademarksofIntegratedDeviceTechnology,Inc. TheST-BUSisatrademarkofMitelCorp.  
MARCH 2003  
1
2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.  
DSC-5716/4  

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