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72V70840DAG8 PDF预览

72V70840DAG8

更新时间: 2024-11-26 14:50:23
品牌 Logo 应用领域
艾迪悌 - IDT /
页数 文件大小 规格书
20页 120K
描述
Telecom IC, PQFP144

72V70840DAG8 技术参数

是否Rohs认证: 符合生命周期:Obsolete
包装说明:QFP, QFP144,.87SQ,20Reach Compliance Code:compliant
风险等级:5.84JESD-30 代码:S-PQFP-G144
JESD-609代码:e3湿度敏感等级:3
端子数量:144最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:QFP封装等效代码:QFP144,.87SQ,20
封装形状:SQUARE封装形式:FLATPACK
电源:3.3 V认证状态:Not Qualified
子类别:Other Telecom ICs最大压摆率:70 mA
标称供电电压:3.3 V表面贴装:YES
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn) - annealed
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUADBase Number Matches:1

72V70840DAG8 数据手册

 浏览型号72V70840DAG8的Datasheet PDF文件第2页浏览型号72V70840DAG8的Datasheet PDF文件第3页浏览型号72V70840DAG8的Datasheet PDF文件第4页浏览型号72V70840DAG8的Datasheet PDF文件第5页浏览型号72V70840DAG8的Datasheet PDF文件第6页浏览型号72V70840DAG8的Datasheet PDF文件第7页 
3.3 VOLT TIME SLOT INTERCHANGE  
DIGITAL SWITCH  
IDT72V70840  
4,096 x 4,096  
Internal Loopback for testing  
Available in 144-pin Thin Quad Flatpack (TQFP) and  
144-pin Ball Grid Array (BGA) packages  
Operating Temperature Range -40°C to +85°C  
3.3V I/O with 5V tolerant inputs and TTL compatible outputs  
ꢀEATURES:  
32 serial input and output streams  
4,096 x 4,096 channel non-blocking switching at 8.192 Mb/s  
Accepts data streams at 2.048 Mb/s, 4.096 Mb/s or 8.192 Mb/s  
Per-channel Variable Delay Mode for low-latency applications  
Per-channel Constant Delay Mode for frame integrity applica-  
tions  
DESCRIPTION:  
Automatic identification of ST-BUS® and GCI serial streams  
Automatic frame offset delay measurement  
Per-stream frame delay offset programming  
Per-channel high impedance output control  
Per-channel processor mode to allow microprocessor writes to  
TXstreams  
The IDT72V70840 has a non-blocking switch capacity of 1,024 x 1,024  
channels at 2.048 Mb/s, 2,048 x 2,048 channels at 4.096 Mb/s, and 4,096 x  
4,096channelsat8.192Mb/s. With32inputsand32outputs,programmable  
per stream control, and a variety of operating modes the IDT72V70840 is  
designed for the TDM time slot interchange function in either voice or data  
applications.  
Direct microprocessor access to all internal memories  
Memory block programming for quick set-up  
IEEE-1149.1 (JTAG) Test Port  
Some of the main features of the IDT72V70840 are low power 3.3 Volt  
operation,automaticST-BUS®/GCIsensing,memoryblockprogramming,  
simplemicroprocessorinterface,onecycledirectinternalmemoryaccesses,  
ꢀUNCTIONAL BLOCK DIAGRAM  
Vcc GND  
RESET  
TRST  
TMS TDI  
TDO TCK  
ODE  
Test Port  
Loopback  
RX0  
RX1  
TX0  
TX1  
TX2  
RX2  
RX3  
TX3  
RX4  
TX4  
RX5  
TX5  
RX6  
TX6  
RX7  
RX8  
TX7  
TX8  
Output  
MUX  
RX9  
TX9  
RX10  
RX11  
RX12  
RX13  
RX14  
RX15  
RX16  
RX17  
RX18  
RX19  
RX20  
RX21  
RX22  
RX23  
RX24  
RX25  
RX26  
RX27  
RX28  
RX29  
RX30  
RX31  
TX10  
TX11  
TX12  
TX13  
TX14  
TX15  
TX16  
TX17  
TX18  
TX19  
TX20  
TX21  
TX22  
TX23  
TX24  
TX25  
TX26  
TX27  
TX28  
TX29  
TX30  
TX31  
Data Memory  
Receive  
Serial Data  
Streams  
Transmit  
Serial Data  
Streams  
Connection  
Memory  
Internal  
Registers  
Timing Unit  
Microprocessor Interface  
5715 drw01  
F0i  
DS  
CS  
DTA  
CLK  
FE/ WFPS  
HCLK  
R/W A0-A13  
D0-D15  
IDTandtheIDTlogoareregisteredtrademarksofIntegratedDeviceTechnology,Inc. TheST-BUS isatrademarkofMitelCorp.  
JANUARY 2002  
1
2001 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.  
DSC-5715/3  

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