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72841L25TFGI8 PDF预览

72841L25TFGI8

更新时间： 2024-02-12 13:05:28
品牌 Logo 应用领域
艾迪悌 - IDT 先进先出芯片
页数 文件大小 规格书
16页 339K
描述
FIFO, 8KX9, 15ns, Synchronous, CMOS, PQFP64, GREEN, SLIM, TQFP-64

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72841L25TFGI8 技术参数

生命周期：Active包装说明：LFQFP,
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.32.00.71风险等级：5.72
最长访问时间：15 ns周期时间：25 ns
JESD-30 代码：S-PQFP-G64长度：10 mm
内存密度：73728 bit内存宽度：9
功能数量：1端子数量：64
字数：8192 words字数代码：8000
工作模式：SYNCHRONOUS最高工作温度：85 °C
最低工作温度：-40 °C组织：8KX9
可输出：YES封装主体材料：PLASTIC/EPOXY
封装代码：LFQFP封装形状：SQUARE
封装形式：FLATPACK, LOW PROFILE, FINE PITCH并行/串行：PARALLEL
座面最大高度：1.6 mm最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：4.5 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子形式：GULL WING
端子节距：0.5 mm端子位置：QUAD
宽度：10 mmBase Number Matches：1

72841L25TFGI8 数据手册

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IDT72801  
IDT72811  
IDT72821  
IDT72831  
IDT72841  
IDT72851  
DUAL CMOS SyncFIFO™  
DUAL 256 x 9, DUAL 512 x 9,  
DUAL 1,024 x 9, DUAL 2,048 x 9,  
DUAL 4,096 x 9, DUAL 8,192 x 9  
Each of the two FIFOs (designated FIFO A and FIFO B) contained in the  
IDT72801/72811/72821/72831/72841/72851hasa9-bitinputdataport(DA0  
-DA8,DB0-DB8)anda9-bitoutputdataport(QA0-QA8,QB0-QB8).Each  
inputportiscontrolledbyafree-runningclock(WCLKA,WCLKB),andtwoWrite  
Enablepins(WENA1,WENA2,WENB1,WENB2). Dataiswrittenintoeachof  
thetwoarraysoneveryrisingclockedgeoftheWriteClock(WCLKA,WCLKB)  
when the appropriate write enable pins are asserted.  
FEATURES:  
•
•
•
•
•
•
The IDT72801 is equivalent to two IDT72201 256 x 9 FIFOs  
The IDT72811 is equivalent to two IDT72211 512 x 9 FIFOs  
The IDT72821 is equivalent to two IDT72221 1,024 x 9 FIFOs  
The IDT72831 is equivalent to two IDT72231 2,048 x 9 FIFOs  
The IDT72841 is equivalent to two IDT72241 4,096 x 9 FIFOs  
The IDT72851 is equivalent to two IDT72251 8,192 x 9 FIFOs  
TheoutputportofeachFIFObankiscontrolledbyitsassociated clockpin  
(RCLKA, RCLKB) and two Read Enable pins (RENA1, RENA2, RENB1,  
RENB2).TheReadClockcanbetiedtotheWriteClockforsingleclockoperation  
orthetwoclockscanrunasynchronousofoneanotherfordualclockoperation.  
An Output Enable pin (OEA, OEB) is provided on the read port of each FIFO  
forthree-stateoutputcontrol.  
• Offers optimal combination of large capacity, high speed,  
design flexibility and small footprint  
• Ideal for prioritization, bidirectional, and width expansion  
applications  
• 10 ns read/write cycle time for the IDT72801/72811/72821/72831/  
72841/72851  
EachofthetwoFIFOshastwofixedflags,Empty(EFA,EFB)andFull(FFA,  
FFB). Twoprogrammableflags,Almost-Empty(PAEA,PAEB)andAlmost-Full  
(PAFA,PAFB),areprovidedforeachFIFObanktoimprovememoryutilization.  
Ifnotprogrammed,theprogrammableflagsdefaulttoempty+7forPAEAand  
PAEB, and full-7 for PAFA and PAFB.  
TheIDT72801/72811/72821/72831/72841/72851architecturelendsitself  
tomanyflexibleconfigurationssuchas:  
• 2-levelprioritydatabuffering  
• Separate control lines and data lines for each FIFO  
• Separate Empty, Full, Programmable Almost-Empty and Almost-  
Full flags for each FIFO  
• Enable puts output data lines in high-impedance state  
• Space-saving 64-pin Thin Quad Flat Pack (TQFP) and Slim Thin  
Quad Flatpack (STQFP)  
•
Industrial temperature range (–40°C to +85°C) is available  
• Green parts available, see ordering information  
• Bidirectional operation  
• Width expansion  
• Depthexpansion  
These FIFOs is fabricated using high-performance submicron CMOS  
technology.  
DESCRIPTION:  
TheIDT72801/72811/72821/72831/72841/72851aredualsynchronous  
(clocked)FIFOs. ThedeviceisfunctionallyequivalenttotwoIDT72201/72211/  
72221/72231/72241/72251 FIFOs in a single package with all associated  
control,data,andflaglinesassignedtoseparatepins.  
FUNCTIONAL BLOCK DIAGRAM  
EFA  
WCLKB  
PAEA  
PAFA  
FFA  
WCLKA  
WENA1  
WENA2  
WENB1  
DA0 - DA8  
DB0 - DB8  
LDA  
LDB  
WENB2  
INPUT REGISTER  
OFFSET REGISTER  
OFFSET REGISTER  
INPUT REGISTER  
EFB  
FLAG  
LOGIC  
WRITE CONTROL  
LOGIC  
FLAG  
LOGIC  
WRITE CONTROL  
LOGIC  
PAEB  
PAFB  
FFB  
RAM ARRAY  
256 x 9, 512 x 9,  
1024 x 9, 2048 x 9,  
4096 x 9, 8192 x 9  
RAM ARRAY  
256 x 9, 512 x 9,  
1024 x 9, 2048 x 9,  
4096 x 9, 8192 x 9  
WRITE POINTER  
READ POINTER  
READ POINTER  
WRITE POINTER  
READ CONTROL  
LOGIC  
READ CONTROL  
LOGIC  
OUTPUT REGISTER  
OUTPUT REGISTER  
RESET LOGIC  
RESET LOGIC  
RCLKB  
RSA  
RSB  
OEA  
OEB  
RCLKA  
RENA1  
RENA2  
RENB1  
QB0 - QB8  
QA0 - QA8  
RENB2  
3034 drw 01  
IDT, IDT logo and the SyncFIFOlogo are registered trademarks of Integrated Device Technology, Inc.  
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGE  
MARCH 2013  
1
©2013 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.  
DSC-3034/6  
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