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72841L15TF PDF预览

72841L15TF

更新时间: 2023-02-26 13:33:27
品牌 Logo 应用领域
艾迪悌 - IDT /
页数 文件大小 规格书
16页 339K
描述
TQFP-64, Tray

72841L15TF 数据手册

 浏览型号72841L15TF的Datasheet PDF文件第2页浏览型号72841L15TF的Datasheet PDF文件第3页浏览型号72841L15TF的Datasheet PDF文件第4页浏览型号72841L15TF的Datasheet PDF文件第6页浏览型号72841L15TF的Datasheet PDF文件第7页浏览型号72841L15TF的Datasheet PDF文件第8页 
IDT72801/728211/72821/72831/72841/72851 DUAL CMOS SyncFIFOTM  
DUAL 256 x 9, DUAL 512 x 9, DUAL 1K x 9, DUAL 2K x 9, DUAL 4K x 9, DUAL 8K x 9  
COMMERCIAL AND INDUSTRIAL  
TEMPERATURERANGES  
ACELECTRICALCHARACTERISTICS  
(Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C; Industrial: VCC = 5V ± 10%, TA = –40°C to +85°C)  
Com'l &  
(1)  
Commercial  
Ind'l  
IDT72801L10  
IDT72811L10  
IDT72821L10  
IDT72831L10  
IDT72841L10  
IDT72851L10  
IDT72801L15  
IDT72811L15  
IDT72821L15  
IDT72831L15  
IDT72841L15  
IDT72851L15  
IDT72801L25  
IDT72811L25  
IDT72821L25  
IDT72831L25  
IDT72841L25  
IDT72851L25  
Symbol  
fS  
Parameter  
Clock Cycle Frequency  
Data Access Time  
Min  
Max.  
100  
6.5  
Min  
Max.  
Min  
Max.  
Unit  
MHz  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
2
2
66.7  
10  
15  
8
2
40  
15  
25  
13  
13  
15  
15  
15  
tA  
tCLK  
tCLKH  
tCLKL  
tDS  
Clock Cycle Time  
10  
4.5  
4.5  
3
15  
6
25  
10  
10  
6
Clock High Time  
Clock Low Time  
6
Data Setup Time  
4
tDH  
Data Hold Time  
0.5  
3
1
1
tENS  
tENH  
tRS  
Enable Setup Time  
4
6
Enable Hold Time  
0.5  
10  
8
1
1
Reset Pulse Width(2)  
15  
10  
10  
0
15  
15  
15  
0
tRSS  
tRSR  
tRSF  
tOLZ  
tOE  
Reset Setup Time  
Reset Recovery Time  
Reset to Flag Time and Output Time  
Output Enable to Output in Low-Z(3)  
Output Enable to Output Valid  
Output Enable to Output in High-Z(3)  
Write Clock to Full Flag  
Read Clock to Empty Flag  
8
0
10  
3
6
3
3
tOHZ  
tWFF  
tREF  
tPAF  
3
6
3
8
3
6.5  
6.5  
6.5  
10  
10  
10  
Write Clock to Programmable  
Almost-Full Flag  
tPAE  
Read Clock to Programmable  
Almost-Empty Flag  
5
6.5  
6
10  
10  
18  
15  
ns  
ns  
ns  
tSKEW1  
tSKEW2  
Skew Time Between Read Clock and  
Write Clock for Empty Flag and Full Flag  
Skew Time Between Read Clock and Write  
Clock for Programmable Almost-Empty Flag  
and Programmable Almost-Full Flag  
14  
15  
NOTES:  
1. Industrial temperature range product for 15ns and 25ns speed grade are available as a standard device.  
2. Pulse widths less than minimum values are not allowed.  
3. Values guaranteed by design, not currently tested.  
5V  
1.1K  
D.U.T.  
AC TEST CONDITIONS  
30pF*  
In Pulse Levels  
GND to 3.0V  
3ns  
680Ω  
InputRise/FallTimes  
InputTimingReferenceLevels  
OutputReferenceLevels  
OutputLoad  
1.5V  
3034 drw 03  
1.5V  
or equivalent circuit  
SeeFigure1  
Figure 1. Output Load  
*Includesjigandscopecapacitances.  
MARCH 2013  
5

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