IDT72801/728211/72821/72831/72841/72851 DUAL CMOS SyncFIFOTM
DUAL 256 x 9, DUAL 512 x 9, DUAL 1K x 9, DUAL 2K x 9, DUAL 4K x 9, DUAL 8K x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
PIN DESCRIPTIONS
TheIDT72801/72811/72821/72831/72841/72851stwoFIFOs, referred descriptiondefinestheinputandoutputsignalsforFIFOA.Thecorrespond-
to as FIFO A and FIFO B, are identical in every respect. The following ing signal names for FIFO B are provided in parentheses.
Symbol
DA0-DA8
DB0-DB8
RSA, RSB
Name
ADataInputs
BDataInputs
Reset
I/O
Description
I
I
I
9-bit data inputs to RAM array A.
9-bit data inputs to RAM array B.
When RSA (RSB) is set LOW, the associated internal read and write pointers of array A (B) are set to
the first location; FFA (FFB) and PAFA (PAFB) go HIGH, and PAEA (PAEB) and EFA (EFB) go
LOW. After power-up, a reset of both FIFOs A and B is required before an initial Write.
WCLKA
WCLKB
WriteClock
I
I
Data is written into the FIFO A (B) on a LOW-to-HIGH transition of WCLKA (WCLKB) when the write
enable(s)areasserted.
WENA1
WENB1
WriteEnable1
If FIFO A (B) is configured to have programmable flags, WENA1 (WENB1) is the only Write
Enable pin that can be used. When WENA1 (WENB1) is LOW, data A (B) is written into the FIFO
on every LOW-to-HIGH transition WCLKA (WCLKB). If the FIFO is configured to have two write enables,
WENA1 (WENB1) must be LOW and WENA2 (WENB2) must be HIGH to write data into the FIFO. Data
will not be written into the FIFO if FFA (FFB) is LOW.
WENA2/LDA
WENB2/LDB
WriteEnable2/
Load
I
FIFO A (B) is configured at reset to have either two write enables or programmable flags. If LDA (LDB)
is HIGH at reset, this pin operates as a second write enable. If WENA2/LDA (WENB2/LDB) is LOW
at reset this pin operates as a control to load and read the programmable flag offsets for its respective array.
If the FIFO is configured to have two write enables, WENA1 (WENB1) must be LOW
and WENA2 (WENB2) must be HIGH to write data into FIFO A (B). Data will not be written into FIFO A (B)
if FFA (FFB) is LOW. If the FIFO is configured to have programmable flags, LDA (LDB) is held LOW to write or
readtheprogrammableflagoffsets.
QA0-QA8
QB0-QB8
ADataOutputs
BDataOutputs
ReadClock
O
O
I
9-bit data outputs from RAM array A.
9-bit data outputs from RAM array B.
RCLKA
RCLKB
Data is read from FIFO A (B) on a LOW-to-HIGH transition of RCLKA (RCLKB) when RENA1
(RENB1) and RENA2 (RENB2) are asserted.
RENA1
RENB1
Read Enable 1
Read Enable 2
OutputEnable
EmptyFlag
I
I
When RENA1 (RENB1) and RENA2 (RENB2) are LOW, data is read from FIFO A (B) on every
LOW-to-HIGH transition of RCLKA (RCLKB). Data will not be read from Array A (B) if EFA (EFB) is LOW.
RENA2
RENB2
When RENA1 (RENB1) and RENA2 (RENB2) are LOW, data is read from the FIFO A (B) on every
LOW-to-HIGH transition of RCLKA (RCLKB). Data will not be read from array A (B) if the EFA (EFB) is LOW.
OEA
OEB
I
When OEA (OEB) is LOW, outputs DA0-DA8 (DB0-DB8) are active. If OEA (OEB) is HIGH, the
outputsDA0-DA8(DB0-DB8)willbeinahigh-impedancestate.
EFA
EFB
O
O
When EFA (EFB) is LOW, FIFO A (B) is empty and further data reads from the output are inhibited.
When EFA (EFB) is HIGH, FIFO A (B) is not empty. EFA (EFB) is synchronized to RCLKA (RCLKB).
PAEA
PAEB
Programmable
Almost-Empty
Flag
When PAEA (PAEB) is LOW, FIFO A (B) is almost-empty based on the offset programmed into the
appropriateoffsetregister. ThedefaultoffsetatresetisEmpty+7. PAEA (PAEB)issynchronizedto
RCLKA (RCLKB).
PAFA
PAFB
Programmable
Almost-FullFlag
O
O
When PAFA (PAFB) is LOW, FIFO A (B) is almost-full based on the offset programmed into the appropriate
offset register. The default offset at reset is Full-7. PAFA (PAFB) is synchronized to WCLKA (WCLKB).
FFA
FFB
VCC
Full Flag
When FFA (FFB) is LOW, FIFO A (B) is full and further data writes into the input are inhibited.
When FFA (FFB) is HIGH, FIFO A (B) is not full. FFA (FFB) is synchronized to WCLKA (WCLKB).
+5V power supply pin.
Power
GND
Ground
0V ground pin.
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