Datasheet > 72615L25PFI

72615L25PFI

更新时间： 2023-04-15 00:00:00

品牌	Logo	应用领域
艾迪悌 - IDT		先进先出芯片
页数	文件大小	规格书
17页	170K
描述
Bi-Directional FIFO, 1KX18, 15ns, Synchronous, CMOS, PQFP64, TQFP-64

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72615L25PFI 数据手册

CMOS SyncBiFIFO^TM

256 x 18 x 2

512 x 18 x 2

IDT72605

IDT72615

DESCRIPTION:

FEATURES:

• Two independent FIFO memories for fully bidirectional data

The IDT72605 and IDT72615 are very high-speed, low-power bidirec-

tionalFirst-In,First-Out(FIFO)memories,withsynchronousinterfaceforfast

readandwritecycletimes.TheSyncBiFIFO™is adatabufferthatcanstore

orretrieveinformationfromtwosourcessimultaneously.TwoDual-PortFIFO

memory arrays are contained in the SyncBiFIFO; one data buffer for each

direction.

transfers

• 256 x 18 x 2 organization (IDT72605)

• 512 x 18 x 2 organization (IDT72615)

• Synchronous interface for fast (20ns) read and write cycle times

• Each data port has an independent clock and read/write control

The SyncBiFIFO has registers on all inputs and outputs. Data is only

transferred into the I/O registers on clock edges, hence the interfaces are

synchronous. EachPorthasitsownindependentclock.Datatransferstothe

I/Oregisters aregatedbytheenablesignals.Thetransferdirectionforeach

portiscontrolledindependentlybyaread/writesignal. Individualoutputenable

signals control whether the SyncBiFIFO is driving the data lines of a port or

whetherthosedatalinesareinahigh-impedancestate.

• Output enable is provided on each port as a three-state control

of the data bus

• Built-in bypass path for direct data transfer between two ports

• Two fixed flags, Empty and Full, for both the A-to-B and the B-

to-A FIFO

• Programmable flag offset can be set to any depth in the FIFO

Bypass controlallows data tobe directlytransferredfrominputtooutput

registerineitherdirection.

• The synchronous BiFIFO is packaged in a 64-pin TQFP (Thin

TheSyncBiFIFOhaseightflags.TheflagpinsareFull,Empty,Almost-Full,

andAlmost-EmptyforbothFIFOmemories.TheoffsetdepthsoftheAlmost-Full

andAlmost-Emptyflagscanbeprogrammedtoanylocation.

TheSyncBiFIFOisfabricatedusingIDT’shigh-speed,submicronCMOS

technology.

Quad Flatpack) and 68-pin PLCC

• Industrial temperature range (–40°C to +85°C)

• Green parts available, see ordering information

FUNCTIONAL BLOCK DIAGRAM

DA0-DA17

R/WA

HIGH

CONTROL

OEA

INPUT REGISTER

OUTPUT REGISTER

MUX

CLK

RESET

LOGIC

A²

µP

A¹

INTERFACE

EFAB

PAEAB

PAFAB

FFAB

MEMORY

ARRAY

512 x 18

256 x 18

EFBA

FLAG

LOGIC

FLAG

LOGIC

ARRAY

512 x 18

256 x 18

PAEBA

PAFBA

FFBA

POWER

SUPPLY

GND

MUX

OUTPUT REGISTER

INPUT REGISTER

CLKB

HIGH

CONTROL

R/W

2704 drw 01

BYPB

DB0-DB17

IDTandtheIDTlogoareregisteredtrademarksofIntegratedDeviceTechnology,Inc.TheSyncBiFIFOisatrademarkofIntegratedDeviceTechnology,Inc.

FEBRUARY 2009

INDUSTRIAL TEMPERATURE RANGE

DSC-2704/9

12 3 4 5 6 7...17

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