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72291L20TFI8 PDF预览

72291L20TFI8

更新时间: 2024-01-17 06:10:51
品牌 Logo 应用领域
艾迪悌 - IDT 时钟先进先出芯片内存集成电路
页数 文件大小 规格书
26页 418K
描述
TQFP-64, Reel

72291L20TFI8 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:TQFP
包装说明:STQFP-64针数:64
Reach Compliance Code:not_compliantECCN代码:EAR99
HTS代码:8542.32.00.71风险等级:5.62
最长访问时间:12 ns其他特性:RETRANSMIT; AUTO POWER DOWN; EASY EXPANDABLE IN DEPTH AND WIDTH
最大时钟频率 (fCLK):50 MHz周期时间:20 ns
JESD-30 代码:S-PQFP-G64JESD-609代码:e0
长度:10 mm内存密度:1179648 bit
内存集成电路类型:OTHER FIFO内存宽度:9
湿度敏感等级:3功能数量:1
端子数量:64字数:131072 words
字数代码:128000工作模式:SYNCHRONOUS
最高工作温度:85 °C最低工作温度:-40 °C
组织:128KX9可输出:YES
封装主体材料:PLASTIC/EPOXY封装代码:LFQFP
封装等效代码:QFP64,.47SQ,20封装形状:SQUARE
封装形式:FLATPACK, LOW PROFILE, FINE PITCH并行/串行:PARALLEL
峰值回流温度(摄氏度):240电源:5 V
认证状态:Not Qualified座面最大高度:1.6 mm
最大待机电流:0.02 A子类别:FIFOs
最大压摆率:0.08 mA最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn85Pb15)
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:20
宽度:10 mm

72291L20TFI8 数据手册

 浏览型号72291L20TFI8的Datasheet PDF文件第1页浏览型号72291L20TFI8的Datasheet PDF文件第2页浏览型号72291L20TFI8的Datasheet PDF文件第4页浏览型号72291L20TFI8的Datasheet PDF文件第5页浏览型号72291L20TFI8的Datasheet PDF文件第6页浏览型号72291L20TFI8的Datasheet PDF文件第7页 
IDT72281/72291  
CMOS SuperSync FIFO™ 65,536 x 9 and 131,072 x 9  
COMMERCIALANDINDUSTRIAL  
TEMPERATURERANGES  
StandardmodeorFWFTmode. TheLDpinselectseitherapartialflagdefault  
settingof127withparallelprogrammingorapartialflagdefaultsettingof1,023  
withserialprogramming. Theflagsareupdatedaccordingtothetimingmode  
anddefaultoffsetsselected.  
DESCRIPTION(CONTINUED)  
FWFTmode. HF,PAEandPAFarealwaysavailableforuse,irrespectiveof  
timingmode.  
The Partial Reset (PRS) also sets the read and write pointers to the first  
locationofthememory. However,thetimingmode,partialflagprogramming  
method,anddefaultorprogrammedoffsetsettingsexistingbeforePartialReset  
remainunchanged.Theflagsareupdatedaccordingtothetimingmodeand  
offsets in effect. PRS is useful for resetting a device in mid-operation, when  
reprogrammingpartialflagswouldbeundesirable.  
TheRetransmitfunctionallowsdatatoberereadfromtheFIFOmorethan  
once. ALOWontheRTinputduringarisingRCLKedgeinitiatesaretransmit  
operationbysettingthereadpointertothefirstlocationofthememoryarray.  
If,atanytime,theFIFOisnotactivelyperforminganoperation,thechipwill  
automaticallypowerdown.Onceinthepowerdownstate,thestandbysupply  
currentconsumptionisminimized. Initiatinganyoperation(byactivatingcontrol  
inputs)willimmediatelytakethedeviceoutofthepowerdownstate.  
The IDT72281/72291 are fabricated using high speed submicron CMOS  
technology.  
PAEandPAFcanbeprogrammedindependentlytoswitchatanypointin  
memory. (SeeTableIandTableII.) Programmableoffsetsdeterminetheflag  
switchingthresholdandcanbeloadedbytwomethods:parallelorserial. Two  
defaultoffsetsettingsarealsoprovided,sothatPAEcanbesettoswitchat127  
or1,023locationsfromtheemptyboundaryandthePAFthresholdcanbeset  
at127or1,023locationsfromthefullboundary. Thesechoicesaremadewith  
the LD pin during Master Reset.  
For serialprogramming,SENtogetherwithLDoneachrisingedgeofWCLK,  
are used to load the offset registers via the Serial Input (SI). For parallel  
programming,WENtogetherwithLDoneachrisingedgeofWCLK,areused  
toloadtheoffsetregistersviaDn. RENtogetherwithLDoneachrisingedge  
ofRCLKcanbeusedtoreadtheoffsetsinparallelfromQnregardlessofwhether  
serialorparalleloffsetloadinghasbeenselected.  
DuringMasterReset(MRS)thefollowingeventsoccur:Thereadandwrite  
pointers are set to the first location of the FIFO. The FWFT pin selects IDT  
PARTIAL RESET (PRS) MASTER RESET (MRS)  
READ CLOCK (RCLK)  
READ ENABLE (REN)  
OUTPUT ENABLE (OE)  
WRITE CLOCK (WCLK)  
WRITE ENABLE (WEN)  
LOAD (LD)  
DATA OUT (Q0 - Qn)  
DATA IN (D0 - Dn)  
IDT  
72281  
72291  
RETRANSMIT (RT)  
SERIAL ENABLE(SEN)  
FIRST WORD FALL THROUGH/SERIAL INPUT  
(FWFT/SI)  
EMPTY FLAG/OUTPUT READY (EF/OR)  
PROGRAMMABLE ALMOST-EMPTY (PAE)  
FULL FLAG/INPUT READY (FF/IR)  
HALF-FULL FLAG (HF)  
PROGRAMMABLE ALMOST-FULL (PAF)  
4675 drw 03  
Figure 1. Block Diagram of Single 65,536 x 9 and 131,072 x 9 Synchronous FIFO  
3

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