Datasheet > 72271LA20PFG

72271LA20PFG

更新时间： 2024-01-12 20:28:17

品牌	Logo	应用领域
艾迪悌 - IDT		时钟先进先出芯片内存集成电路
页数	文件大小	规格书
27页	440K
描述
FIFO, 32KX9, 12ns, Synchronous, CMOS, PQFP64, GREEN, PLASTIC, TQFP-64

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技术参数
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72271LA20PFG 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Active	零件包装代码：	QFP
包装说明：	LQFP, QFP64,.66SQ,32	针数：	64
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.32.00.71	风险等级：	5.19
最长访问时间：	12 ns	其他特性：	RETRANSMIT; AUTO POWER DOWN; EASY EXPANDABLE IN DEPTH AND WIDTH
最大时钟频率 (fCLK)：	50 MHz	周期时间：	20 ns
JESD-30 代码：	S-PQFP-G64	JESD-609代码：	e3
长度：	14 mm	内存密度：	294912 bit
内存集成电路类型：	OTHER FIFO	内存宽度：	9
湿度敏感等级：	3	功能数量：	1
端子数量：	64	字数：	32768 words
字数代码：	32000	工作模式：	SYNCHRONOUS
最高工作温度：	70 °C	最低工作温度：
组织：	32KX9	可输出：	YES
封装主体材料：	PLASTIC/EPOXY	封装代码：	LQFP
封装等效代码：	QFP64,.66SQ,32	封装形状：	SQUARE
封装形式：	FLATPACK, LOW PROFILE	并行/串行：	PARALLEL
峰值回流温度（摄氏度）：	260	电源：	5 V
认证状态：	Not Qualified	座面最大高度：	1.6 mm
最大待机电流：	0.02 A	子类别：	FIFOs
最大压摆率：	0.075 mA	最大供电电压 (Vsup)：	5.5 V
最小供电电压 (Vsup)：	4.5 V	标称供电电压 (Vsup)：	5 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子面层：	Matte Tin (Sn) - annealed
端子形式：	GULL WING	端子节距：	0.8 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	30
宽度：	14 mm	Base Number Matches：	1

72271LA20PFG 数据手册

IDT72261LA/72271LA SuperSyncFIFO™

16,384 x 9 and 32,768 x 9

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

areusedtoloadtheoffsetregistersviaDn. RENtogetherwithLDoneachrising

edgeofRCLKcanbeusedtoreadtheoffsetsinparallelfromQnregardless

ofwhetherserialorparalleloffsetloadinghasbeenselected.

DuringMasterReset(MRS)thefollowingeventsoccur:Thereadandwrite

pointers are set to the first location of the FIFO. The FWFT pin selects IDT

StandardmodeorFWFTmode. TheLDpinselectseitherapartialflagdefault

settingof127withparallelprogrammingorapartialflagdefaultsettingof1,023

withserialprogramming. Theflagsareupdatedaccordingtothetimingmode

anddefaultoffsetsselected.

The Partial Reset (PRS) also sets the read and write pointers to the first

location of the memory. However, the timing mode, partial flag program-

ming method, and default or programmed offset settings existing before

Partial Reset remain unchanged. The flags are updated according to the

timing mode and offsets in effect. PRS is useful for resetting a device in

mid-operation, when reprogramming partial flags would be undesirable.

The Retransmit function allows data to be reread from the FIFO more

than once. A LOW on the RT input during a rising RCLK edge initiates a

retransmit operation by setting the read pointer to the first location of the

memory array.

DESCRIPTION (CONTINUED)

InFWFTmode, thefirstwordwrittentoanemptyFIFOisclockeddirectly

to the data output lines after three transitions of the RCLK signal. A REN

does not have to be asserted for accessing the first word. However,

subsequent words written to the FIFO do require a LOW on REN for

access. The state of the FWFT/SI input during Master Reset determines

the timing mode in use.

For applications requiring more data storage capacity than a single

FIFO can provide, the FWFT timing mode permits depth expansion by

chaining FIFOs in series (i.e. the data outputs of one FIFO are connected

to the corresponding data inputs of the next). No external logic is required.

These FIFOs have five flag pins, EF/OR (Empty Flag or Output Ready),

FF/IR (Full Flag or Input Ready), HF (Half-full Flag), PAE (Programmable

Almost-Empty flag) and PAF (Programmable Almost-Full flag). The EF

and FF functions are selected in IDT Standard mode. The IR and OR

functions are selected in FWFT mode. HF, PAE and PAF are always

available for use, irrespective of timing mode.

PAE and PAF can be programmed independently to switch at any point

in memory. (See Table I and Table II.) Programmable offsets determine

the flag switching threshold and can be loaded by two methods: parallel or

serial. Two default offset settings are also provided, so that PAE can be

set to switch at 127 or 1,023 locations from the empty boundary and the

PAF threshold can be set at 127 or 1,023 locations from the full boundary.

These choices are made with the LD pin during Master Reset.

For serial programming, SEN together with LD on each rising edge of

WCLK, are used to load the offset registers via the Serial Input (SI). For

parallelprogramming,WENtogetherwithLDoneachrisingedgeofWCLK,

If, at any time, the FIFO is not actively performing an operation, the chip

will automatically power down. Once in the power down state, the standby

supply current consumption is minimized. Initiating any operation (by

activating control inputs) will immediately take the device out of the power

down state.

The IDT72261LA/72271LA are fabricated using high speed submicron

CMOStechnology.

PARTIAL RESET (PRS) MASTER RESET (MRS)

READ CLOCK (RCLK)

READ ENABLE (REN)

OUTPUT ENABLE (OE)

WRITE CLOCK (WCLK)

WRITE ENABLE (WEN)

LOAD (LD)

DATA OUT (Q0 - Qn)

DATA IN (D0 - Dn)

IDT

72261LA

72271LA

RETRANSMIT (RT)

SERIAL ENABLE(SEN)

FIRST WORD FALL THROUGH/SERIAL INPUT

(FWFT/SI)

EMPTY FLAG/OUTPUT READY (EF/OR)

PROGRAMMABLE ALMOST-EMPTY (PAE)

FULL FLAG/INPUT READY (FF/IR)

HALF FULL FLAG (HF)

PROGRAMMABLE ALMOST-FULL (PAF)

4671 drw 03

Figure 1. Block Diagram of Single 16,384 x 9 and 32,768 x 9 Synchronous FIFO

1 234 5 6 7...27

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与72271LA20PFG相关器件

型号	品牌	描述	获取价格	数据表
72271LA20PFG8	IDT	CMOS SuperSync FIFO	获取价格
72271LA20PFGI	IDT	FIFO, 32KX9, 12ns, Synchronous, CMOS, PQFP64, GREEN, PLASTIC, TQFP-64	获取价格
72271LA20PFGI8	IDT	CMOS SuperSync FIFO	获取价格
72271LA20PFI9	IDT	FIFO, 32KX9, 12ns, Synchronous, CMOS, PQFP64, PLASTIC, TQFP-64	获取价格
72271LA20TFG	IDT	CMOS SuperSync FIFO	获取价格
72271LA20TFG8	IDT	CMOS SuperSync FIFO	获取价格

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