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72271LA15PFG8 PDF预览

72271LA15PFG8

更新时间： 2024-01-16 16:22:25
品牌 Logo 应用领域
艾迪悌 - IDT 先进先出芯片
页数 文件大小 规格书
27页 446K
描述
CMOS SuperSync FIFO

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72271LA15PFG8 技术参数

是否Rohs认证： 符合生命周期：Active
包装说明：LQFP,Reach Compliance Code：compliant
ECCN代码：EAR99HTS代码：8542.32.00.71
风险等级：5.18最长访问时间：10 ns
其他特性：RETRANSMIT; AUTO POWER DOWN; EASY EXPANDABLE IN DEPTH AND WIDTH周期时间：15 ns
JESD-30 代码：S-PQFP-G64长度：14 mm
内存密度：294912 bit内存宽度：9
功能数量：1端子数量：64
字数：32768 words字数代码：32000
工作模式：SYNCHRONOUS最高工作温度：70 °C
最低工作温度：组织：32KX9
可输出：YES封装主体材料：PLASTIC/EPOXY
封装代码：LQFP封装形状：SQUARE
封装形式：FLATPACK, LOW PROFILE并行/串行：PARALLEL
峰值回流温度（摄氏度）：260座面最大高度：1.6 mm
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：4.5 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子形式：GULL WING端子节距：0.8 mm
端子位置：QUAD处于峰值回流温度下的最长时间：30
宽度：14 mmBase Number Matches：1

72271LA15PFG8 数据手册

 浏览型号72271LA15PFG8的Datasheet PDF文件第1页浏览型号72271LA15PFG8的Datasheet PDF文件第2页浏览型号72271LA15PFG8的Datasheet PDF文件第3页浏览型号72271LA15PFG8的Datasheet PDF文件第5页浏览型号72271LA15PFG8的Datasheet PDF文件第6页浏览型号72271LA15PFG8的Datasheet PDF文件第7页 
IDT72261LA/72271LA SuperSyncFIFO™  
16,384 x 9 and 32,768 x 9  
COMMERCIALANDINDUSTRIAL  
TEMPERATURERANGES  
PIN DESCRIPTION  
Symbol  
D0–D8  
MRS  
Name  
I/O  
Description  
DataInputs  
I
I
Datainputsfora9-bitbus.  
MasterReset  
MRSinitializesthereadandwritepointerstozeroandsetstheoutputregistertoallzeroes.  
During Master Reset, the FIFO is configured for either FWFT or IDT Standard mode, one of  
two programmable flag default settings, and serial or parallel programming of the offset settings.  
PRS  
RT  
Partial Reset  
Retransmit  
I
I
PRS initializes the read and write pointers to zero and sets the output method (serial or parallel),  
and programmable flag settings are all retained.  
RT asserted on the rising edge of RCLK initializes the READ pointer to zero, sets the EF flag to  
LOW (OR to HIGH in FWFT mode) temporarily and does not disturb the write pointer, programming  
method, existing timing mode or programmable flag settings. RT is useful to reread data from the  
first physical location of the FIFO.  
FWFT/SI  
WCLK  
First Word Fall  
Write Clock  
I
I
During Master Reset, selects First Word Fall Through or IDT Standard mode. Through/Serial  
In After Master Reset, this pin functions as a serial input for loading offset registers  
When enabled by WEN, the rising edge of WCLK writes data into the FIFO and offsets into  
the programmable registers for parallel programming, and when enabled by SEN, the rising  
edge of WCLK writes one bit of data into the programmable register for serial programming.  
WEN  
Write Enable  
Read Clock  
I
I
WEN enables WCLK for writing data into the FIFO memory and offset registers.  
RCLK  
When enabled by REN, the rising edge of RCLK reads data from the FIFO memory and offsets  
fromtheprogrammableregisters.  
REN  
OE  
Read Enable  
OutputEnable  
SerialEnable  
Load  
I
I
I
I
REN enablesRCLKforreadingdatafromtheFIFOmemoryandoffsetregisters.  
OEcontrolstheoutputimpedanceofQn.  
SEN  
LD  
SENenablesserialloadingofprogrammableflagoffsets.  
During Master Reset, LD selects one of two partial flag default offsets (127 or 1,023) and determines  
the flag offset programming method, serial or parallel. After Master Reset, this pin enables writing to  
andreadingfromtheoffsetregisters.  
DC  
Don't Care  
I
This pin must be tied to either VCC or GND and must not toggle after Master Reset.  
FF/IR  
Full Flag/  
Input Ready  
O
In the IDT Standard mode, the FF function is selected. FF indicates whether or not the FIFO memory  
is full. In the FWFT mode, the IR function isselected. IR indicates whether or not there is space  
availableforwritingtotheFIFOmemory.  
EF/OR  
PAF  
EmptyFlag/  
OutputReady  
O
O
O
In the IDT Standard mode, the EF function is selected. EF indicates whether or not the FIFO memory  
isempty. In FWFT mode, the OR function is selected. OR indicates whether or not there is valid data  
availableattheoutputs.  
Programmable  
Almost-FullFlag  
PAF goes LOW if the number of words in the FIFO memory is more than word capacity of the FIFO  
minusthefulloffsetvaluem,whichisstoredintheFullOffsetregister.Therearetwopossibledefault  
values for m: 127 or 1,023.  
PAE  
Programmable  
Almost-EmptyFlag  
PAE goes LOW if the number of words in the FIFO memory is less than offset n, which is stored in the  
Empty Offset register. There are two possible default values for n: 127 or 1,023. Other values for n  
canbeprogrammedintothedevice.  
HF  
Half-FullFlag  
DataOutputs  
Power  
O
O
HF indicateswhethertheFIFOmemoryismoreorlessthanhalf-full.  
Dataoutputsfora9-bus  
Q0–Q8  
VCC  
+5 Volt power supply pins.  
GND  
Ground  
Groundpins.  
4
1234567...27

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