Datasheet > 72271LA10TFGI8

72271LA10TFGI8

更新时间： 2022-02-26 09:10:14

品牌	Logo	应用领域
艾迪悌 - IDT		先进先出芯片
页数	文件大小	规格书
27页	446K
描述
CMOS SuperSync FIFO

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数据手册

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72271LA10TFGI8 数据手册

3.3 VOLT CMOS SuperSync FIFO^™

16,384 x 9

32,768 x9

IDT72261LA

IDT72271LA

ADDENDUM

DIFFERENCES BETWEEN THE IDT72261LA/72271LA AND IDT72261L/72271L

IDT has improved the performance of the IDT72261/72271 SuperSync™ FIFOs. The new versions are designated by the “LA” mark. The LA part

is pin-for-pin compatible with the original “L” version. Some difference exist between the two versions. The following table details these differences.

Item

NEW PART

OLD PART

Comments

IDT72261LA

IDT72271LA

IDT72261L

IDT72271L

Pin #3

DC (Don’t Care) - There is

no restriction on WCLK and

RCLK. See note 1.

FS (Frequency Select)

In the LA part this pin must be tied

to either VCC or GND and must

not toggle after reset.

First Word Latency

(IDT Standard Mode)

60ns⁽²⁾+ tREF + 1 TRCLK⁽⁴⁾

60ns⁽²⁾+ tREF + 2 TRCLK⁽⁴⁾

60ns⁽²⁾+ tREF + 1 TRCLK⁽⁴⁾

60ns⁽²⁾+ tREF + 2 TRCLK⁽⁴⁾

tFWL₁= 10*Tf⁽³⁾+ 2TRCLK⁽⁴⁾(ns) First word latency in the LA part

is a fixed value, independent of

the frequency of RCLK or WCLK.

tFWL₂= 10*Tf⁽³⁾+ 3TRCLK⁽⁴⁾(ns) First word latency in the LA part

is a fixed value, independent of

the frequency of RCLK or WCLK.

tRTF₁= 14*Tf⁽³⁾+ 3TRCLK⁽⁴⁾(ns) Retransmit latency in the LA part

is a fixed value, independent of

the frequency of RCLK or WCLK.

tRTF₂= 14*Tf⁽³⁾+ 4TRCLK⁽⁴⁾(ns) Retransmit latency in the LA part

is a fixed value, independent of

First Word Latency

(FWFT Mode)

Retransmit Latency

(IDT Standard Mode)

Retransmit Latency

(FWFT Mode)

the frequency of RCLK or WCLK.

ICC1

75mA

20mA

150mA

15mA

Active supply current

Standby current

ICC2

Typical ICC1⁽⁵⁾

15 + 1.85*fS + 0.02*CL*fS(mA) Not Given

Typical ICC1 Current calculation

NOTES:

1. WCLK and RCLK can vary independently and can be stopped. There is no restriction on operating WCLK and RCLK.

2. This is tSKEW3.

3. Tf is the period of the ‘selected clock’.

4. TRCLK is the cycle period of the read clock.

5. Typical ICC1 is based on VCC = 5V, tA = 25C, fS = WCLK frequency = RCLK frequency (in MHz using TTL levels), data switching at fS/2, CL = Capacitive Load (in pF).

IDT, IDT logo are registered trademarks of Integrated Device Technology, Inc.The SuperSync FIFO is a trademark of Integrated Device Technology, Inc.

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