IDT72421/72201/72211/72221/72231/72241/72251 CMOS SyncFIFO™
64 x 9, 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
OUTPUTENABLE(OE)
SIGNALDESCRIPTIONS
WhenOutputEnable (OE)is enabled(LOW), the paralleloutputbuffers
receivedatafromtheoutputregister. WhenOutputEnable(OE)is disabled
(HIGH),theQoutputdatabusisinahigh-impedancestate.
INPUTS:
DATA IN (D0 - D8)
Datainputsfor9-bitwidedata.
WRITE ENABLE 2/LOAD (WEN2/LD)
This is a dual-purpose pin. The FIFO is configured at Reset to have
programmableflagsortohavetwowriteenables,whichallowsdepthexpansion.
IfWriteEnable2/Load(WEN2/LD)issetHIGHatReset(RS=LOW),thispin
operates as a second write enable pin.
If the FIFO is configured to have two write enables, when Write Enable
(WEN1)is LOWandWrite Enable 2/Load(WEN2/LD)is HIGH, data canbe
loadedintotheinputregisterandRAMarrayontheLOW-to-HIGHtransition
ofeveryWriteClock(WCLK). DataisstoredintheRAMarraysequentiallyand
independentlyofanyongoingreadoperation.
CONTROLS:
RESET (RS)
ResetisaccomplishedwhenevertheReset(RS)inputistakentoaLOW
state. During reset, both internal read and write pointers are set to the first
location. Aresetisrequiredafterpower-upbeforeawriteoperationcantake
place. TheFullFlag(FF)andProgrammableAlmost-Fullflag(PAF)willbereset
toHIGHaftertRSF. TheEmptyFlag(EF)andProgrammableAlmost-Empty
flag(PAE)willberesettoLOWaftertRSF. Duringreset,theoutputregisteris
initializedtoallzerosandtheoffsetregistersareinitializedtotheirdefaultvalues.
In this configuration, when Write Enable (WEN1) is HIGH and/or Write
Enable2/Load(WEN2/LD)isLOW,theinputregisterholdsthepreviousdata
and no new data is allowed to be loaded into the register.
WRITE CLOCK (WCLK)
Topreventdataoverflow,theFullFlag(FF)willgoLOW,inhibitingfurther
writeoperations. Uponthecompletionofavalidreadcycle,theFullFlag(FF)
willgoHIGHaftertWFF,allowingavalidwritetobegin. WriteEnable1(WEN1)
and Write Enable 2/Load (WEN2/LD) are ignored when the FIFO is full.
TheFIFOisconfiguredtohaveprogrammableflagswhentheWriteEnable
2/Load(WEN2/LD)is setLOWatReset(RS=LOW). TheIDT72421/72201/
72211/72221/72231/72241/72251devicescontainfour8-bitoffsetregisters
whichcanbeloadedwithdataontheinputs,orreadontheoutputs. SeeFigure
3fordetailsofthesizeoftheregistersandthedefaultvalues.
IftheFIFOisconfiguredtohaveprogrammableflagswhentheWriteEnable
1(WEN1)andWriteEnable2/Load(WEN2/LD)aresetLOW,dataontheinputs
DiswrittenintotheEmpty(LeastSignificantBit)OffsetregisteronthefirstLOW-
to-HIGHtransitionoftheWriteClock(WCLK). DataiswrittenintotheEmpty(Most
SignificantBit)OffsetregisteronthesecondLOW-to-HIGHtransitionoftheWrite
Clock(WCLK),intotheFull(LeastSignificantBit)Offsetregisteronthethird
transition,andintotheFull(MostSignificantBit)Offsetregisteronthefourth
transition. ThefifthtransitionoftheWriteClock(WCLK)againwritestotheEmpty
(LeastSignificantBit)Offsetregister.
AwritecycleisinitiatedontheLOW-to-HIGHtransitionoftheWriteClock
(WCLK). DatasetupandholdtimesmustbemetinrespecttotheLOW-to-HIGH
transition of WCLK. The Full Flag (FF) and Programmable Almost-Full flag
(PAF)aresynchronizedwithrespecttotheLOW-to-HIGHtransitionofWCLK.
The Write andReadClocks canbe asynchronous orcoincident.
WRITE ENABLE 1 (WEN1)
IftheFIFOisconfiguredforprogrammableflags,WriteEnable1(WEN1)
istheonlyenablecontrolpin. Inthisconfiguration,whenWriteEnable1(WEN1)
isLOW,datacanbeloadedintotheinputregisterandRAMarrayontheLOW-
to-HIGHtransitionofeveryWriteClock(WCLK). DataisstoredintheRAMarray
sequentiallyandindependentlyofanyongoingreadoperation.
Inthisconfiguration,whenWriteEnable1(WEN1)isHIGH,theinputregister
holdsthepreviousdataandnonewdataisallowedtobeloadedintotheregister.
IftheFIFOisconfiguredtohavetwowriteenables,whichallowsfordepth
expansion,therearetwoenablecontrolpins. SeeWriteEnable2paragraph
belowforoperationinthisconfiguration.
Topreventdataoverflow,theFullFlag(FF)willgoLOW,inhibitingfurther
writeoperations. Uponthecompletionofavalidreadcycle,theFullFlag(FF)
willgoHIGHaftertWFF,allowingavalidwritetobegin. WriteEnable1(WEN1)
is ignored when the FIFO is full.
However,writingalloffsetregistersdoesnothavetooccuratonetime. One
ortwooffsetregisterscanbewrittenandthenbybringingtheWriteEnable2/
Load (WEN2/LD) pin HIGH, the FIFO is returned to normal read/write
operation. WhentheWriteEnable2/Load(WEN2/LD)pinissetLOW,theWrite
Enable1(WEN1)isLOW,thenextoffsetregisterinsequenceiswritten.
READ CLOCK (RCLK)
DatacanbereadontheoutputsontheLOW-to-HIGHtransitionoftheRead
Clock(RCLK). TheEmptyFlag(EF)andProgrammableAlmost-Emptyflag
(PAE)aresynchronizedwithrespecttotheLOW-to-HIGHtransitionofRCLK.
The Write andReadClocks canbe asynchronous orcoincident.
LD
0
WEN1
0
WCLK
Selection
EmptyOffset(LSB)
Empty Offset (MSB)
Full Offset (LSB)
Full Offset (MSB)
READ ENABLES (REN1, REN2)
WhenbothReadEnables(REN1,REN2)areLOW,dataisreadfromthe
RAMarraytotheoutputregisterontheLOW-to-HIGHtransitionoftheRead
Clock (RCLK).
WheneitherReadEnable(REN1,REN2)isHIGH,theoutputregisterholds
the previous data and no new data is allowed to be loaded into the register.
Whenallthe data has beenreadfromthe FIFO, the EmptyFlag(EF)will
goLOW,inhibitingfurtherreadoperations. Onceavalidwriteoperationhas
beenaccomplished, the EmptyFlag(EF)willgoHIGHaftertREF anda valid
readcanbegin. TheReadEnables(REN1,REN2)areignoredwhentheFIFO
isempty.
0
1
1
0
1
No Operation
Write Into FIFO
No Operation
1
NOTE:
1. For the purposes of this table, WEN2 = VIH.
2. The same selection sequence applies to reading from the registers. REN1 and REN2
are enabled and read is performed on the LOW-to-HIGH transition of RCLK.
Figure 2. Write Offset Register
©
OCTOBER22,2008
5
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