IDT72205LB/72215LB/72225LB/72235LB/72245LBCMOSSyncFIFOTM
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
OUTPUTENABLE(OE)
SIGNALDESCRIPTIONS:
When Output Enable (OE) is enabled (LOW), the parallel output buffers
receivedatafromtheoutputregister.WhenOEisdisabled(HIGH),theQoutput
databusisinahigh-impedancestate.
INPUTS:
DATA IN (D0 - D17)
Datainputsfor18-bitwidedata.
LOAD (LD)
The IDT72205LB/72215LB/72225LB/72235LB/72245LB devices con-
taintwo12-bitoffsetregisterswithdataontheinputs,orreadontheoutputs.
WhentheLoad(LD)pinissetLOWandWENissetLOW, dataontheinputs
D0-D11 is written into the Empty Offset register on the first LOW-to-HIGH
transition of the Write Clock (WCLK). When the LD pin and (WEN) are held
LOWthendataiswrittenintotheFullOffsetregisteronthesecondLOW-to-HIGH
transitionof(WCLK).Thethirdtransitionofthewriteclock(WCLK)againwrites
totheEmptyOffsetregister.
However,writingalloffsetregistersdoesnothavetooccuratonetime.One
ortwooffsetregisterscanbewrittenandthenbybringingtheLDpinHIGH,the
FIFOisreturnedtonormalread/writeoperation.WhentheLDpinissetLOW,
andWENisLOW,thenextoffsetregisterinsequenceiswritten.
CONTROLS:
RESET (RS)
ResetisaccomplishedwhenevertheReset(RS)inputistakentoaLOWstate.
Duringreset,bothinternalreadandwritepointersaresettothefirstlocation.
Aresetisrequiredafterpower-upbeforeawriteoperationcantakeplace.The
FullFlag(FF),Half-FullFlag(HF)andProgrammableAlmost-FullFlag(PAF)
will be reset to HIGH after tRSF. The Empty Flag (EF) and Programmable
Almost-EmptyFlag(PAE)willberesettoLOWaftertRSF. Duringreset,theoutput
registerisinitializedtoallzerosandtheoffsetregistersareinitializedtotheirdefault
values.
WRITE CLOCK (WCLK)
AwritecycleisinitiatedontheLOW-to-HIGHtransitionoftheWriteClock
(WCLK).DatasetupandholdtimesmustbemetwithrespecttotheLOW-to-HIGH
transitionofWCLK.
LD
WEN
WCLK
Selection
Writingtooffsetregisters:
EmptyOffset
0
0
The Write and Read Clocks can be asynchronous or coincident.
FullOffset
WRITE ENABLE (WEN)
0
1
1
0
1
NoOperation
WhentheWENinput isLOWandLDinputisHIGH,datamaybeloadedinto
the FIFO RAM array on the rising edge of every WCLK cycle if the device is
notfull. DataisstoredintheRAMarraysequentiallyandindependentlyofany
ongoing read operation.
WhenWENisHIGH,nonewdataiswrittenintheRAMarrayoneachWCLK
cycle.
Topreventdataoverflow,FFwillgoLOW,inhibitingfurtherwriteoperations.
Uponthecompletionofavalidreadcycle,FFwillgoHIGHallowingawriteto
occur. The FF flag is updated on the rising edge of WCLK. WEN is ignored
when the FIFO is full.
WriteIntoFIFO
NoOperation
1
NOTE:
1. The same selection sequence applies to reading from the registers. REN is enabled and
read is performed on the LOW-to-HIGH transition of RCLK.
Figure 2. Write Offset Register
READ CLOCK (RCLK)
DatacanbereadontheoutputsontheLOW-to-HIGHtransitionoftheRead
Clock (RCLK), when Output Enable (OE) is set LOW.
The Write and Read Clocks can be asynchronous or coincident.
17
17
0
11
11
EMPTY OFFSET REGISTER
READ ENABLE (REN)
WhenReadEnableisLOWandLDinputisHIGH,dataisloadedfromthe
RAM array into the output register on the rising edge of every RCLK cycle if
thedeviceisnotempty.
WhentheRENinputisHIGH,theoutputregisterholdsthepreviousdataand
nonewdataisloadedintotheoutputregister. ThedataoutputsQ0-Qnmaintain
the previous data value.
DEFAULT VALUE
001FH (72205) 003FH (72215):
007FH (72225/72235/72245)
0
FULL OFFSET REGISTER
Every word accessed at Qn, including the first word written to an empty
FIFO,mustberequestedusingREN. Whenthelastwordhasbeenreadfrom
theFIFO,theEmptyFlag(EF)willgoLOW,inhibitingfurtherreadoperations.
REN is ignored when the FIFO is empty. Once a write is performed, EF will
go HIGH allowing a read to occur. The EF flag is updated on the rising edge
ofRCLK.
DEFAULT VALUE
001FH (72205) 003FH (72215):
007FH (72225/72235/72245)
2766 drw 05
NOTE:
1. Any bits of the offset register not being programmed should be set to zero.
Figure 3. Offset Register Location and Default Values
6
MARCH 2013
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